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| MC68HC711D3 MC68HC11D3 MC68HC11D0 MC68L11D0 Data Sheet HC11 Microcontrollers MC68HC711D3 Rev. 2.1 07/2005 freescale.com MC68HC711D3 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level Description Reformatted to current publications standards Removed references to PROG mode. Corrected pin assignments for: Figure 1-2. Pin Assignments for 40-Pin Plastic DIP Figure 1-3. Pin Assignments for 44-Pin PLCC Added Figure 1-4. Pin Assignments for 44-Pin QFP September, 2003 2 1.9 Interrupt Request (IRQ) -- Reworked description for clarity. 2.4 Programmable Read-Only Memory (PROM) -- Updated with additional data. Section 10. Ordering Information and Mechanical Specifications -- Added mechanical specifications for 44-pin plastic quad flat pack (QFP). Added the following appendices: Appendix A. MC68HC11D3 and MC68HC11D0 Appendix B. MC68L11D0 July, 2005 2.1 Updated to meet Freescale identity guidelines. Page Number(s) N/A Throughout 4 5 6 7 13 133 137 143 Throughout MC68HC711D3 Data Sheet, Rev. 2.1 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Operating Modes and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 4 Resets, Interrupts, and Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 5 Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 6 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Chapter 7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 8 Programmable Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 10 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 121 Appendix A MC68HC11D3 and MC68HC11D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Appendix B MC68L11D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 5 List of Chapters MC68HC711D3 Data Sheet, Rev. 2.1 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply (VDD, VSS, and EVSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Driver and External Clock Input (XTAL and EXTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . E-Clock Output (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . MODA and MODB (MODA/LIR and MODB/VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Bit 6/Address Strobe (PD6/AS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Lines (PA7-PA0, PB7-PB0, PC7-PC0, and PD7-PD0) . . . . . . . . . . . . . . . . . . . 13 13 13 14 16 16 16 16 17 18 18 18 18 18 Chapter 2 Operating Modes and Memory 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 2.4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Bootstrap Mode (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Read-Only Memory (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming an Individual EPROM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the EPROM with Downloaded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Programming Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 22 23 23 23 29 30 31 31 32 32 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 7 Table of Contents Chapter 3 Central Processor Unit (CPU) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.1 Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.2 Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.3 Zero (Z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.4 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.5 I-Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.6 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.7 X-Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6.8 STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Opcodes and Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 34 34 34 36 36 36 36 36 37 37 37 37 37 37 38 38 38 38 39 39 39 39 39 Chapter 4 Resets, Interrupts, and Low-Power Modes 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Bits in the CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Highest Priority I Interrupt and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . . . . . . 47 47 47 47 47 48 48 49 51 51 51 51 52 58 MC68HC711D3 Data Sheet, Rev. 2.1 8 Freescale Semiconductor 4.4 4.4.1 4.4.2 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Chapter 5 Input/Output (I/O) Ports 5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 62 62 63 63 63 63 64 64 64 Chapter 6 Serial Communications Interface (SCI) 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 65 68 68 68 69 69 69 70 70 71 72 75 Chapter 7 Serial Peripheral Interface (SPI) 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 9 77 77 77 79 79 79 80 Table of Contents 7.5.3 7.5.4 7.6 7.7 7.7.1 7.7.2 7.7.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 80 81 81 82 83 Chapter 8 Programmable Timer 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.5 8.5.1 8.5.2 8.5.3 8.6 8.7 8.7.1 8.7.2 8.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Timer Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Computer Operating Properly Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 9 Electrical Characteristics 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 105 106 106 107 109 114 MC68HC711D3 Data Sheet, Rev. 2.1 10 Freescale Semiconductor 9.8 9.9 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 10 Ordering Information and Mechanical Specifications 10.1 10.2 10.3 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-Pin DIP (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-Pin PLCC (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-Pin QFP (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122 123 Appendix A MC68HC11D3 and MC68HC11D0 A.1 A.2 A.3 A.4 A.5 A.5.1 A.5.2 A.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC11D3 and MC68HC11D0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 126 127 128 128 128 128 129 Appendix B MC68L11D0 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 MC68L11D0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.1 Functional Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.2 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.3 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.4 Peripheral Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.5 Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.6 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 131 131 131 133 133 134 135 136 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 11 Table of Contents MC68HC711D3 Data Sheet, Rev. 2.1 12 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction This section depicts the general characteristics and features of the MC68HC711D3 high-density complementary metal-oxide semiconductor (HCMOS) microcontroller unit (MCU). The MC68HC711D3 contains highly sophisticated on-chip peripheral functions. This high-speed, low-power programmable read-only memory (PROM) MCU has a nominal bus speed of 3 MHz. The fully static design allows operations at frequencies down to dc. The MC68HC11D3 and MC68HC11D0 are read-only memory (ROM) based high-performance microcontrollers (MCU) based on the MC68HC11E9 design. The MC68L11D0 is an extended-voltage version of the MC68HC11D0 that can operate in applications that require supply voltages as low as 3.0 V. The information in this document pertains to all the devices with the exceptions noted in Appendix A MC68HC11D3 and MC68HC11D0 and Appendix B MC68L11D0. 1.2 Features Features of the MC68HC711D3 include: * Expanded 16-bit timer system with four-stage programmable prescaler * Non-return-to-zero (NRZ) serial communications interface (SCI) * Power-saving stop and wait modes * 64 Kbytes memory addressability * Multiplexed address/data bus * Serial peripheral interface (SPI) * 4 Kbytes of one-time programmable read-only memory (OTPROM) * 8-bit pulse accumulator circuit * 192 bytes of static random-access memory (RAM) (all saved during standby) * Real-time interrupt (RTI) circuit * Computer operating properly (COP) watchdog system * Available in these packages: - 40-pin plastic dual in-line package (DIP) - 44-pin plastic leaded chip carrier (PLCC) - 44-pin plastic quad flat pack (QFP) 1.3 Structure Refer to Figure 1-1, which shows the structure of the MC68HC711D3 MCU. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 13 General Description MODA/LIR MODB/VSTBY NOT BONDED IN 40-PIN PACKAGE RESET IRQ XIRQ/VPP XTAL EXTAL E OSCILLATOR MODE CONTROL PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 INTERRUPT CONTROL CLOCK LOGIC 4 KBYTES EPROM OR OTPROM PORT A COP PAI/OC1 PULSE ACCUMULATOR OC2/OC1 OC3/OC1 OC4/OC1 TIMER IC4/OC5/OC1 IC1 IC2 IC3 PERIODIC INTERRUPT 192 BYTES STATIC RAM SERIAL PERIPHERAL INTERFACE (SPI) SERIAL COMMUNICATIONS INTERFACE (SCI) MOSI MISO SCK VDD VSS EVSS MC68HC711D3 CPU CORE SS TxD RxD MULTIPLEXED ADDRESS/DATA BUS DATA DIRECTION REGISTER B PORT B DATA DIRECTION REGISTER C PORT C DATA DIRECTION REGISTER D PORT D PD6/AS PD5 PD4 PD3 PD2 PD1 Figure 1-1. MC68HC711D3 Block Diagram 1.4 Pin Descriptions Refer to Figure 1-2, Figure 1-3, and Figure 1-4 for pin assignments. MC68HC711D3 Data Sheet, Rev. 2.1 14 Freescale Semiconductor PD7/R/W PC7 PC6 PC5 PC4 PC3 PC2 PC1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC0 PD0 Pin Descriptions VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 XIRQ/VPP PD7/R/W PD6/AS RESET IRQ PD0 PD1 PD2 PD3 PD4 PD5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 XTAL EXTAL E MODA/LIR MODB/VSTBY PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA5 PA7 VDD Figure 1-2. Pin Assignments for 40-Pin Plastic DIP MODB/VSTBY 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 VDD PA7 PA6 PA5 PA4 PA3 PD2 PD3 PD4 PD5 PA2 28 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC PA0 PA1 6 5 4 3 2 44 43 42 PC4 PC5 PC6 PC7 XIRQ/VPP PD7/R/W PD6/AS RESET IRQ PD0 PD1 7 8 9 10 11 12 13 14 15 16 17 Figure 1-3. Pin Assignments for 44-Pin PLCC MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 15 1 41 MODA/LIR EXTAL XTAL EVSS PC3 PC2 PD1 PC0 VSS E General Description EXTAL MODA 35 MODB 34 XTAL 38 EVSS PC3 PC2 PC1 PC0 VSS 43 42 41 40 39 37 36 E PC4 PC5 PC6 PC7 XIRQ PD7 PD6 RESET IRQ PD0 PD1 1 2 3 4 5 6 7 8 9 10 12 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC PA0 PA1 32 31 30 29 28 27 26 25 24 13 14 15 16 17 18 19 20 21 PA3 23 PA7 PA6 PA5 PA4 PD2 PD3 PD4 PD5 Figure 1-4. Pin Assignments for 44-Pin QFP 1.5 Power Supply (VDD, VSS, and EVSS) Power is supplied to the MCU through VDD and VSS. VDD is the power supply (+5 V 10%) and VSS is ground (0 V). EVSS, available on the 44-pin PLCC and QFP, is an additional ground pin. 1.6 Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit. In addition, the state of this pin is one of the factors governing the selection of BOOT mode. 1.7 Crystal Driver and External Clock Input (XTAL and EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins is four times higher than the desired E-clock rate. Refer to Figure 1-5 for crystal and clock connections. 1.8 E-Clock Output (E) E is the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E-clock output is one fourth that of the input frequency at the XTAL and EXTAL pins. The E clock can be turned off in single-chip mode for greater noise immunity if desired. See 4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO) for details. MC68HC711D3 Data Sheet, Rev. 2.1 16 Freescale Semiconductor PA2 VDD Interrupt Request (IRQ) MCU EXTAL 4xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR XTAL NC OR 10K-100K LOAD FIRST MCU 25 pF * EXTAL 10 M XTAL 4xE CRYSTAL 25 pF * NC OR 10K-100K LOAD SECOND MCU EXTAL XTAL MCU 25 pF * EXTAL 10 M XTAL 4xE CRYSTAL 25 pF * * Values includes all stray capacitances. Figure 1-5. Oscillator Connections 1.9 Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the microcontroller unit (MCU). Either negative edge-sensitive triggering or level-sensitive triggering is program selectable by using the IRQE bit of the OPTION register. IRQ is always configured to level-sensitive triggering at reset. While the programmable read-only memory (PROM) is being programmed, this pin provides the chip enable (CE) signal. To prevent accidental programming of the PROM during reset, an external resistor is required on IRQ to pull the pin to VDD. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 17 General Description 1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP) The XIRQ input provides the capability for asynchronously applying non-maskable interrupts to the MCU after a power-on reset (POR). During reset, the X bit in the condition code register (CCR) is set masking any interrupt until enabled by software. This level-sensitive input requires an external pullup resistor to VDD. In the programming configuration of the bootstrap mode, this pin is used to supply one-time programmable read-only memory (OTPROM) programming voltage, VPP, to the MCU. To avoid programming accidents during reset, this pin should be equal to VDD during normal operation unless XIRQ is active. 1.11 MODA and MODB (MODA/LIR and MODB/VSTBY) As reset transitions, these pins are used to latch the part into one of the four central processor unit (CPU) controlled modes of operation. The LIR output can be used as an aid to debugging once reset is completed. The open-drain LIR pin goes to an active low during the first E-clock cycle of each instruction and remains low for the duration of that cycle. The VSTBY input is used to retain random-access memory (RAM) contents during power down. 1.12 Read/Write (R/W) This pin performs either of two separate functions, depending on the operating mode. * In single-chip and bootstrap modes, R/W functions as input/output port D bit 7. Refer to Chapter 5 Input/Output (I/O) Ports for further information. * In expanded multiplexed and test modes, R/W performs a read/write function. R/W controls the direction of transfers on the external data bus. 1.13 Port D Bit 6/Address Strobe (PD6/AS) This pin performs either of two separate functions, depending on the operating mode. * In single-chip and bootstrap modes, the pin functions as input/output port D bit 6. * In the expanded multiplexed and test modes, it provides an address strobe (AS) function. AS is used to demultiplex the address and data signals at port C. Refer to Chapter 2 Operating Modes and Memory for further information. 1.14 Input/Output Lines (PA7-PA0, PB7-PB0, PC7-PC0, and PD7-PD0) In the 44-pin PLCC package, 32 input/output lines are arranged into four 8-bit ports: A, B, C, and D. The lines of ports B, C, and D are fully bidirectional. Port A has two bidirectional, three input-only, and three output-only lines in the 44-pin PLCC packaging. In the 40-pin DIP, two of the output-only lines are not bonded. Each of these four ports serves a purpose other than input/output (I/O), depending on the operating mode or peripheral functions selected. NOTE Ports B, C, and two bits of port D are available for I/O functions only in single-chip and bootstrap modes. MC68HC711D3 Data Sheet, Rev. 2.1 18 Freescale Semiconductor Input/Output Lines (PA7-PA0, PB7-PB0, PC7-PC0, and PD7-PD0) Refer to Table 1-1 for details about the functions of the 32 port signals within different operating modes. Table 1-1. Port Signal Functions Port/Bit PA0 PA1 PA2 PA3 PA4 (1) Single-Chip and Bootstrap Mode PA0/IC3 PA1/IC2 PA2/IC1 Expanded Multiplexed and Special Test Mode PA3/OC5/IC4/and-or OC1 PA4/OC4/and-or OC1 PA5/OC3/and-or OC1 PA6/OC2/and-or OC1 PA7/PAI/and-or OC1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS PD6 PD7 AS R/W A8 A9 A10 A11 A12 A13 A14 A15 A0/D0 A1/D1 A2/D2 A3/D3 A4/D4 A5/D5 A6/D6 A7/D7 PA5 PA6 (1) PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1. In the 40-pin package, pins PA4 and PA6 are not bonded. Their associated I/O and output compare functions are not available externally. They can still be used as internal software timers, however. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 19 General Description MC68HC711D3 Data Sheet, Rev. 2.1 20 Freescale Semiconductor Chapter 2 Operating Modes and Memory 2.1 Introduction This section contains information about: * The modes that define MC68HC711D3 operating conditions * The on-chip memory that allows the microcontroller unit (MCU) to be configured for various applications * The 4-Kbytes of programmable read-only memory (PROM) 2.2 Operating Modes The MC68HC711D3 uses two dedicated pins, MODA and MODB, to select one of two normal operating modes or one of two special operating modes. A value reflecting the microcontroller unit (MCU) status or mode selected is latched on bits SMOD and MDA of the highest priority I-bit interrupt and miscellaneous register (HPRIO) on the rising edge of reset. The normal operating modes are the single-chip and expanded-multiplexed modes. The special operating modes are the bootstrap and test modes. Table 2-1 shows mode selection according to the values encoded on the MODA and MODB pins, and the value latched in the SMOD and MDA bits. Table 2-1. Mode Selection RESET 1 1 1 1 0 MODA 0 1 0 1 0 MODB 1 1 0 0 0 Mode Selected Normal -- single chip Normal -- expanded multiplexed Special -- bootstrap (BOOT) Special -- test Reserved SMOD 0 0 1 1 X MDA 0 1 0 1 X 2.2.1 Single-Chip Mode In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address or data bus. The 4-Kbyte erasable programmable read-only memory (EPROM) would contain all program code and is located at $F000-$FFFF. This mode provides maximum use of the pins for on-chip peripheral functions, and all the address and data activity occurs within the MCU. 2.2.2 Expanded Multiplexed Mode In the expanded-multiplexed mode, the MCU can address up to 64 Kbytes of address space. High-order address bits are output on the port B pins. Low-order address bits and the bidirectional data bus are multiplexed on port C. The AS pin provides the control output used in demultiplexing the low-order address. The R/W pin is used to control the direction of data transfer on the port C bus. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 21 Operating Modes and Memory If this mode is entered out of reset, the EPROM is located at $7000-$7FFF and vector accesses are from external memory. To be in expanded-multiplexed mode with EPROM located at $F000-$FFFF, it is necessary to start in single-chip mode, executing out of EPROM, and then set the MDA bit of the HPRIO register to switch mode. NOTE R/W, AS, and the high-order address bus (port B) are inputs in single-chip mode. These inputs may need to be pulled up so that off-chip accesses cannot occur while the MCU is in single-chip mode. 2.2.3 Special Bootstrap Mode (BOOT) This special mode is similar to single-chip mode. The resident bootloader program contains a 256-byte program in a special on-chip read-only memory (ROM). The user downloads a small program into on-board RAM using the SCI port. Program control is passed to RAM when an idle line of at least four characters occurs. In this mode, all interrupt vectors are mapped to RAM (see Table 2-2), so that the user can set up a jump table, if desired. Bootstrap mode (BOOT) is entered out of reset if the voltage level on both MODA and MODB is low. The programming aspect of bootstrap mode, used to program the one-time programmable ROM (OTPROM) through the MCU, is entered automatically if IRQ is low and programming voltage is available on the VPP pin. IRQ should be pulled up while in reset with MODA and MODB configured for bootstrap mode to prevent unintentional programming of the EPROM. This versatile mode (BOOT) can be used for test and diagnostic functions on completed modules and for programming the on-board PROM. The serial receive logic is initialized by software in the bootloader ROM, which provides program control for the SCI baud rate and word format. Mode switching to other modes can occur under program control by writing to the SMOD and MDA bits of the HPRIO register. Two special bootloader functions allow either an immediate jump-to-RAM at memory address $0000 or an immediate jump-to-EPROM at $F000. Table 2-2. Bootstrap Mode Jump Vectors Address 00C4 00C7 00CA 00CD 00D0 00D3 00D6 00D9 00DC 00DF 00E3 00E5 00E8 SCI SPI Pulse accumulator input edge Pulse accumulator overflow Timer overflow Timer output compare 5/input capture 4 Timer output compare 4 Timer output compare 3 Timer output compare 2 Timer output compare 1 Timer input capture 3 Timer input capture 2 Timer input capture 1 Vector MC68HC711D3 Data Sheet, Rev. 2.1 22 Freescale Semiconductor Memory Map Table 2-2. Bootstrap Mode Jump Vectors (Continued) Address 00EB 00EE 00F1 00F4 00F7 00FA 00FD BF00 (Boot) Real-time interrupt IRQ XIRQ SWI Illegal opcode COP fail Clock monitor Reset Vector 2.2.4 Special Test Mode This special expanded mode is primarily intended or production testing. The user can access a number of special test control bits in this mode. Reset and interrupt vectors are fetched externally from locations $BFC0-$BFFF. A switch can be made from this mode to other modes under program control. 2.3 Memory Map Figure 2-1 illustrates the memory map for both normal modes of operation (single-chip and expanded-multiplexed), as well as for both special modes of operation (bootstrap and test). * In the single-chip mode, the MCU does not generate external addresses. The internal memory locations are shown in the shaded areas, and the contents of these shaded areas are explained on the right side of the diagram. * In expanded-multiplexed mode, the memory locations are basically the same as in the single-chip mode except that the memory locations between shaded areas are for externally addressed memory and I/O. * The special bootstrap mode is similar to the single-chip mode, except that the bootstrap program ROM is located at memory locations $BF00-$BFFF, vectors included. * The special test mode is similar to the expanded-multiplexed mode except the interrupt vectors are at external memory locations. 2.3.1 Control and Status Registers Figure 2-2 is a representation of all 64 bytes of control and status registers, I/O and data registers, and reserved locations that make up the internal register block. This block may be mapped to any 4-K boundary in memory, but reset locates it at $0000-$003F. This mappability factor and the default starting addresses are indicated by the use of a bold 0 as the starting character of a register's address. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 23 Operating Modes and Memory $0000 $1000 $2000 $3000 $4000 $5000 $6000 $7000 $8000 $9000 $A000 $B000 $C000 $D000 $E000 $F000 $FFFF SINGLE CHIP EXPANDED SPECIAL MULTIPLEXED BOOTSTRAP SPECIAL TEST EXTERNAL EXTERNAL $0000 INTERNAL REGISTERS AND I/O (MAY BE MAPPED TO ANY 4-K BOUNDARY $003F USING INIT REGISTER) $0040 192 BYTES STATIC RAM (MAY BE MAPPED TO ANY 4-K BOUNDARY $00FF USING THE INIT REGISTER) $7000 4 KBYTES PROM (ROM) PRESENT AT RESET AND MAY BE DISABLED BY $7FFF EPON (ROM ON) BIT IN CONFIG REGISTER. INTERRUPT VECTORS ARE EXTERNAL. $BF00 $BFFF 256-BYTES BOOT ROM $BFC0 SPECIAL MODES INTERRUPT $BFFF VECTORS NORMAL MODES INTERRUPT $BFFF VECTORS $BF00 $BFFF 4-KBYTES PROM (ROM) $BFC0 MODB 1 1 0 0 MODA 0 1 0 1 Mode Selected Single-chip (mode 0) Expanded multiplexed (mode 1) Special bootstrap Special test Figure 2-1. MC68HC711D3 Memory Map MC68HC711D3 Data Sheet, Rev. 2.1 24 Freescale Semiconductor Memory Map Addr. $0000 $0001 Register Name Port A Data Register Read: (PORTA) Write: See page 61. Reset: Reserved Port C Control Register Read: (PIOC) Write: See page 63. Reset: Port C Data Register Read: (PORTC) Write: See page 63. Reset: Port B Data Register Read: (PORTB) Write: See page 62. Reset: Reserved Data Direction Register Read: for Port B (DDRB) Write: See page 62. Reset: Data Direction Register Read: for Port C (DDRC) Write: See page 63. Reset: Port D Data Register Read: (PORTD) Write: See page 64. Reset: Data Direction Register Read: for Port D (DDRD) Write: See page 64. Reset: Reserved Timer Compare Force Register Read: (CFORC) Write: See page 93. Reset: Output Compare 1 Mask Register Read: (OC1M) Write: See page 93. Reset: Output Compare 1 Data Register Read: (OC1D) Write: See page 94. Reset: Bit 7 PA7 Hi-Z R 0 0 PC7 6 PA6 0 R 0 0 PC6 5 PA5 0 R CWOM 0 PC5 4 PA4 0 R 0 0 PC4 3 PA3 Hi-Z R 0 0 PC3 2 PA2 Hi-Z R 0 0 PC2 1 PA1 Hi-Z R 0 0 PC1 Bit 0 PA0 Hi-Z R 0 0 PC0 $0002 $0003 Reset configures pins as Hi-Z inputs PB7 PB6 PB5 PB4 PB3 BP2 BP1 PB0 $0004 $0005 Reset configures pins as Hi-Z inputs R DDB7 0 DDC7 0 PD7 0 DDD7 0 R FOC1 0 OC1M7 0 OC1D7 0 R DDB6 0 DDC6 0 PD6 0 DDD6 0 R FOC2 0 OC1M6 0 OC1D6 0 R DDB5 0 DDC5 0 PD5 0 DDD5 0 R FOC3 0 OC1M5 0 OC1D5 0 R DDB4 0 DDC4 0 PD4 0 DDD4 0 R FOC4 0 OC1M4 0 OC1D4 0 R R DDB3 0 DDC3 0 PD3 0 DDD3 0 R FOC5 0 OC1M3 0 OC1D3 0 = Reserved R DDB2 0 DDC2 0 PD2 0 DDD2 0 R 0 0 0 0 0 0 R DDB1 0 DDC1 0 PD1 0 DDD1 0 R 0 0 0 0 0 0 U = Unaffected R DDB0 0 DDC0 0 PD0 0 DDD0 0 R 0 0 0 0 0 0 $0006 $0007 $0008 $0009 $000A $000B $000C $000D = Unimplemented Figure 2-2. Register and Control Bit Assignments (Sheet 1 of 5) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 25 Operating Modes and Memory Addr. $000E Register Name Timer Counter Register High Read: (TCNT) Write: See page 94. Reset: Timer Counter Register Low Read: (TCNT) Write: See page 94. Reset: Timer Input Capture Register 1 Read: High (TIC1) Write: See page 89. Reset: Timer Input Capture Register 1 Read: Low (TIC1) Write: See page 89. Reset: Timer Input Capture Register 2 Read: High (TIC2) Write: See page 89. Reset: Timer Input Capture Register 2 Read: Low (TIC2) Write: See page 89. Reset: Timer Input Capture Register 3 Read: High (TIC3) Write: See page 89. Reset: Timer Input Capture Register 3 Read: Low (TIC3) Write: See page 89. Reset: Timer Output Compare Register 1 Read: High (TOC1) Write: See page 92. Reset: Timer Output Compare Register 1 Read: Low (TOC1) Write: See page 92. Reset: Timer Output Compare Register 2 Read: High (TOC2) Write: See page 92. Reset: Timer Output Compare Register 2 Read: Low (TOC2) Write: See page 92. Reset: Bit 7 Bit 15 0 Bit 7 0 Bit 15 6 Bit 14 0 Bit 6 0 Bit 14 5 Bit 13 0 Bit 5 0 Bit 13 4 Bit 12 0 Bit 4 0 Bit 12 3 Bit 11 0 Bit 3 0 Bit 11 2 Bit 10 0 Bit 2 0 Bit 10 1 Bit 9 0 Bit 1 0 Bit 9 Bit 0 Bit 8 0 Bit 0 0 Bit 8 $000F $0010 Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0011 Unaffected by reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0012 Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0013 Unaffected by reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0014 Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0015 Unaffected by reset Bit 15 1 Bit 7 1 Bit 15 1 Bit 7 1 Bit 14 1 Bit 6 1 Bit 14 1 Bit 6 1 Bit 13 1 Bit 5 1 Bit 13 1 Bit 5 1 Bit 12 1 Bit 4 1 Bit 12 1 Bit 4 1 R Bit 11 1 Bit 3 1 Bit 11 1 Bit 3 1 = Reserved Bit 10 1 Bit 2 1 Bit 10 1 Bit 2 1 Bit 9 1 Bit 1 1 Bit 9 1 Bit 1 1 U = Unaffected Bit 15 1 Bit 0 1 Bit 8 1 Bit 0 1 $0016 $0017 $0018 $0019 = Unimplemented Figure 2-2. Register and Control Bit Assignments (Sheet 2 of 5) MC68HC711D3 Data Sheet, Rev. 2.1 26 Freescale Semiconductor Memory Map Addr. Register Name Timer Output Compare Register 3 Read: High (TOC3) Write: See page 92. Reset: Timer Output Compare Register 3 Read: Low (TOC3) Write: See page 92. Reset: Timer Output Compare Register 4 Read: High (TOC4) Write: See page 92. Reset: Timer Output Compare Register 4 Read: Low (TOC4) Write: See page 92. Reset: Timer Input Capture 4/ Read: Output Compare 5 Register High Write: (TI4/O5) See page 90. Reset: Timer Input Capture 4/ Read: Output Compare 5 Register Low Write: (TI4/O5) See page 90. Reset: Timer Control 1 Register Read: (TCTL1) Write: See page 95. Reset: Timer Control Register 2 Read: (TCTL2) Write: See page 89. Reset: Timer Interrupt Mask 1 Register Read: (TMSK1) Write: See page 95. Reset: Timer Interrupt Flag 1 Register Read: (TFLG1) Write: See page 96. Reset: Timer Interrupt Mask 2 Register Read: (TMSK2) Write: See page 96. Reset: Timer Interrupt Flag 2 Register Read: (TFLG2) Write: See page 97. Reset: Bit 7 Bit 15 1 Bit 7 1 Bit 15 1 Bit 7 1 Bit 15 6 Bit 14 1 Bit 6 1 Bit 14 1 Bit 6 1 Bit 14 5 Bit 13 1 Bit 5 1 Bit 13 1 Bit 5 1 Bit 13 4 Bit 12 1 Bit 4 1 Bit 12 1 Bit 4 1 Bit 12 3 Bit 11 1 Bit 3 1 Bit 11 1 Bit 3 1 Bit 11 2 Bit 10 1 Bit 2 1 Bit 10 1 Bit 2 1 Bit 10 1 Bit 9 1 Bit 1 1 Bit 9 1 Bit 1 1 Bit 9 Bit 0 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 Bit 8 $001A $001B $001C $001D $001E 1 Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $001F 1 OM2 0 EDG4B 0 OC1I 0 OC1F 0 TOI 0 TOF 0 1 OL2 0 EDG4A 0 OC2I 0 OC2F 0 RTII 0 RTIF 0 1 OM3 0 EDG1B 0 OC3I 0 OC3F 0 PAOVI 0 PAOVF 0 1 OL3 0 EDG1A 0 OC4I 0 OC4F 0 PAII 0 PAIF 0 R 1 OM4 0 EDG2B 0 I4/O5I 0 I4/O5F 0 0 0 0 0 = Reserved 1 OL4 0 EDG2A 0 IC1I 0 IC1F 0 0 0 0 0 1 OM5 0 EDG3B 0 IC2I 0 IC2F 0 PR1 0 0 0 U = Unaffected 1 OL5 0 EDG3A 0 IC3I 0 IC3F 0 PR0 0 0 0 $0020 $0021 $0022 $0023 $0024 $0025 = Unimplemented Figure 2-2. Register and Control Bit Assignments (Sheet 3 of 5) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 27 Operating Modes and Memory Addr. $0026 Register Name Pulse Accumulator Control Read: Register (PACTL) Write: See pages 99 and 102. Reset: Pulse Accumulator Count Register Read: (PACNT) Write: See page 103. Reset: SPI Control Register Read: (SPCR) Write: See page 81. Reset: SPI Status Register Read: (SPSR) Write: See page 82. Reset: SPI Data I/O Register Read: (SPDR) Write: See page 83. Reset: Baud Rate Register Read: (BAUD) Write: See page 72. Reset: SCI Control Register 1 Read: (SCCR1) Write: See page 70. Reset: SCI Control Register 2 Read: (SCCR2) Write: See page 70. Reset: SCI Status Register Read: (SCSR) Write: See page 71. Reset: SCI Data Register Read: (SCDR) Write: See page 69. Reset: Reserved Bit 7 DDRA7 0 Bit 7 6 PAEN 0 Bit 6 5 PAMOD 0 Bit 5 4 PEDGE 0 Bit 4 3 DDRA3 0 Bit 3 2 I4/O5 0 Bit 2 1 RTR1 0 Bit 1 Bit 0 RTR0 0 Bit 0 $0027 Unaffected by reset SPIE 0 SPIF 0 Bit 7 SPE 0 WCOL 0 Bit 6 DWOM 0 0 0 Bit 5 MSTR 0 MODF 0 Bit 4 CPOL 0 0 0 Bit 3 CPHA 1 0 0 Bit 2 SPR1 U 0 0 Bit 1 SPR0 U 0 0 Bit 0 $0028 $0029 $002A Unaffected by reset TCLR 0 R8 U TIE 0 TDRE 1 R7/T7 0 0 T8 U TCIE 0 TC 1 R6/T6 SCP1 0 0 0 RIE 0 RDRF 0 R5/T5 SCP0 0 M 0 ILIE 0 IDLE 0 R4/T4 RCKB 0 WAKE 0 TE 0 OR 0 R3/T3 SCR2 U 0 0 RE 0 NF 0 R2/T2 SCR1 U 0 0 RWU 0 FE 0 R1/T1 SCR0 U 0 0 SBK 0 0 0 R0/T0 $002B $002C $002D $002E $002F $0030 $0038 Unaffected by reset R R R R R R R R $0039 System Configuration Options Read: Register (OPTION) Write: See page 49. Reset: 0 0 0 0 IRQE 0 DLY 1 R CME 0 = Reserved 0 0 CR1 0 U = Unaffected CR0 0 = Unimplemented Figure 2-2. Register and Control Bit Assignments (Sheet 4 of 5) MC68HC711D3 Data Sheet, Rev. 2.1 28 Freescale Semiconductor Memory Map Addr. $003A Register Name Arm/Reset COP Timer Circuitry Read: Register (COPRST) Write: See page 48. Reset: PROM Programming Control Read: Register (PPROG) Write: See page 32. Reset: Highest Priority I-Bit Interrupt and Read: Miscellaneous Register (HPRIO) Write: See page 58. Reset: Bit 7 Bit 7 0 MBE 0 RBOOT 6 Bit 6 0 0 0 SMOD Note 1 5 Bit 5 0 ELAT 0 MDA 4 Bit 4 0 EXCOL 0 IRVNE 3 Bit 3 0 EXROW 0 PSEL3 0 2 Bit 2 0 0 0 PSEL2 1 1 Bit 1 0 0 0 PSEL1 0 Bit 0 Bit 0 0 PGM 0 PSEL0 1 $003B $003C 1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the mode during initialization. Refer to Table 4-3. Hardware Mode Select Summary. $003D RAM and I/O Mapping Register Read: (INIT) Write: See page 29. Reset: Read: Test 1 Register Write: (TEST) Reset: System Configuration Register Read: (CONFIG) Write: See page 30. Reset: RAM3 0 TILOP 0 0 0 RAM2 0 0 0 0 0 RAM1 0 OCC4 0 0 0 RAM0 0 CBYP 0 0 0 R REG3 0 DISR 0 0 0 = Reserved REG2 0 FCM 0 NOCOP U REG1 0 FCOP 0 ROMON U U = Unaffected REG0 1 0 0 0 0 $003E $003F = Unimplemented Figure 2-2. Register and Control Bit Assignments (Sheet 5 of 5) 2.3.2 RAM and I/O Mapping Register The random-access memory (RAM) and input/output (I/O) mapping register (INIT) is a special-purpose 8-bit register that is used during initialization to change the default locations of RAM and control registers within the MCU memory map. It can be written to only once within the first 64 E-clock cycles after a reset in normal modes. Thereafter, it becomes a read-only register. Address: Read: Write: Reset: $003D Bit 7 RAM3 0 6 RAM2 0 5 RAM1 0 4 RAM0 0 3 REG3 0 2 REG2 0 1 REG1 0 Bit 0 REG0 0 Figure 2-3. RAM and I/O Mapping Register (INIT) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 29 Operating Modes and Memory RAM2-RAM0 (INIT bits 7-4) specify the starting address for the 192 bytes of static RAM. REG3-REG0 (INIT bits 3-0) specify the starting address for the control and status register block. In each case, the four RAM or REG bits become the four upper bits of the 16-bit address of the RAM or register. Since the INIT register is set to $00 by reset, the internal registers begin at $0000 and RAM begins at $0040. Throughout this document, control and status register addresses are displayed with the high-order digit shown as a bold 0. This convention indicates that the register block may be relocated to any 4-K memory page, but that its default location is $0000. RAM and the control and status registers can be relocated independently. If the control and status registers are relocated in such a way as to conflict with PROM, then the register block takes priority, and the EPROM or OTPROM at those locations becomes inaccessible. No harmful conflicts result. Lower priority resources simply become inaccessible. Similarly, if an internal resource conflicts with an external device, no harmful conflict results, since data from the external device is not applied to the internal data bus. Thus, it cannot interfere with the internal read. NOTE There are unused register locations in the 64-byte control and status register block. Reads of these unused registers return data from the undriven internal data bus, not from another source that happens to be located at the same address. 2.3.3 Configuration Control Register The configuration control register (CONFIG) controls the presence of OTPROM or EPROM in the memory map and enables the computer operating properly (COP) watchdog system. This register is writable only once in expanded and single-chip modes (SMOD = 0). In these mode, the COP watchdog timer is enabled out of reset. In all modes, except normal expanded, EPROM is enabled and located at $F000-$FFFF. In normal expanded mode, EPROM is enabled and located at $7000-$7FFF. Should the user wish to be in expanded mode, but with EPROM mapped at $F000-$FFFF, he must reset in single-chip mode, and write a 1 to the MDA bit in the HPRIO register. Address: $003F Bit 7 Read: Write: Reset: 0 0 U = Unaffected 6 0 0 5 0 0 4 0 0 3 0 0 2 NOCOP U 1 ROMON U Bit 0 0 0 Figure 2-4. Configuration Control Register (CONFIG) Bits 7-3 and 0 -- Not implemented Always read 0. NOCOP -- Computer Operating Properly System Disable Bit This bit is cleared out of reset in normal modes (single chip and expanded), enabling the COP system. It is writable only once after reset in these modes (SMOD = 0). In the special modes (test and bootstrap) (SMOD = 1), this bit comes out of reset set, and is writable any time. 1 = COP system is disabled. 0 = COP system is enabled, reset forced on timeout. MC68HC711D3 Data Sheet, Rev. 2.1 30 Freescale Semiconductor Programmable Read-Only Memory (PROM) ROMON -- PROM Enable Bit This bit is set out of reset, enabling the EPROM or OTPROM in all modes. This bit is writable once in normal modes (SMOD = 0), but is writable at any time in special modes (SMOD = 1). 1 = PROM is present in the memory map. 0 = PROM is disabled from the memory map. NOTE In expanded mode out of reset, the EPROM or OTPROM is located at $7000-$7FFF. In all other modes, the PROM resides at $F000-$FFFF. 2.4 Programmable Read-Only Memory (PROM) The MC68HC711D3 has 4-Kbytes of one-time programmable read-only memory (OTPROM). The PROM address is $F000-$FFFF in all modes except expanded multiplexed. In expanded- multiplexed mode, the PROM is located at $7000-$7FFF after reset. The on-chip read-only memory (ROM) of an MC68HC711D3 is programmed in MCU mode. In this mode, the PROM is programmed through the MCU in the bootstrap or test modes. The erased state of a PROM byte is $FF. Using the on-chip OTPROM programming feature requires an external 12-volt nominal power supply (VPP). Normal programming is accomplished using the OTPROM programming register (PPROG). As described in the following subsections, these two methods of programming and verifying EPROM are possible: 1. Programming an individual EPROM address 2. Programming the EPROM with downloaded data 2.4.1 Programming an Individual EPROM Address In this method, the MCU programs its own EPROM by controlling the PPROG register. Use these procedures to program the EPROM through the MCU with: * The ROMON bit set in the CONFIG register * The 12-volt nominal programming voltage present on the XIRQ/VPP pin * The IRQ pin must be pulled high. EPROG LDAB STAB STAA LDAB STAB JSR CLR #$20 $003B $0,X #$21 $003B DLYEP $003B Set ELAT bit (PGM = 0) to enable EPROM latches. Store data to EPROM address Set PGM bit with ELAT = 1 to enable EPROM programming voltage Delay 2-4 ms Turn off programming voltage and set to READ mode MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 31 Operating Modes and Memory 2.4.2 Programming the EPROM with Downloaded Data When using this method, the EPROM is programmed by software while in the special test or bootstrap modes. User-developed software can be uploaded through the SCI or a ROM-resident EPROM programming utility can be used. The 12-volt nominal programming voltage must be present on the XIRQ/VPP pin. To use the resident utility, bootload a 3-byte program consisting of a single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming utility. The utility program sets the X and Y index registers to default values, then receives programming data from an external host, and puts it in EPROM. The value in IX determines programming delay time. The value in IY is a pointer to the first address in EPROM to be programmed (default = $F000). When the utility program is ready to receive programming data, it sends the host the $FF character. Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting with the first location in the EPROM array. After the last byte to be programmed is sent and the corresponding verification data is returned, the programming operation is terminated by resetting the MCU. 2.4.3 PROM Programming Control Register The PROM programming control register (PPROG) is used to control the programming of the OTPROM or EPROM. PPROG is cleared on reset so that the PROM is configured for normal read. Address: $003B Bit 7 Read: Write: Reset: MBE 0 6 0 0 5 ELAT 0 4 EXCOL 0 3 EXROW 0 2 0 0 1 0 0 Bit 0 PGM 0 Figure 2-5. PROM Programming Control Register (PPROG) MBE -- Multiple Byte Program Enable Bit This bit is reserved for testing. Bit 6, 2, and 1 -- Not implemented Always read 0. ELAT -- EPROM (OTPROM) Latch Control Bit 1 = PROM address and data bus are configured for programming. Writes to PROM cause address and data to be latched. The PROM cannot be read. 0 = PROM address and data bus are configured for normal reads. PROM cannot be programmed. EXCOL -- Select Extra Columns Bit This bit is reserved for testing. EXROW -- Select Extra Row Bit This bit is reserved for testing. PGM -- EPROM (OTPROM) Program Command Bit This bit may be written only when ELAT = 1. 1 = Programming power is switched on to PROM array. 0 = Programming power is switched off. MC68HC711D3 Data Sheet, Rev. 2.1 32 Freescale Semiconductor Chapter 3 Central Processor Unit (CPU) 3.1 Introduction This section presents information on M68HC11 central processor unit (CPU): * Architecture * Data types * Addressing modes * Instruction set * Special operations such as subroutine calls and interrupts The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. I/O has no instructions separate from those used by memory. This architecture also allows accessing an operand from an external memory location with no execution time penalty. 3.2 CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed in the following paragraphs, are shown in Figure 3-1. 7 15 15 15 15 15 ACCUMULATOR A 07 ACCUMULATOR B DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER 7 CONDITION CODE REGISTER SXH 0 0 0 0 0 0 0 I N Z V C A:B D IX IY SP PC CCR CARRY OVERFLOW ZERO NEGATIVE I INTERRUPT MASK HALF CARRY (FROM BIT 3) X INTERRUPT MASK STOP DISABLE Figure 3-1. Programming Model MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 33 Central Processor Unit (CPU) 3.2.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators A or B interchangeably, these exceptions apply: * The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents of 16-bit register X or Y, but there are no equivalent instructions that use A instead of B. * The TAP and TPA instructions transfer data from accumulator A to the condition code register or from the condition code register to accumulator A. However, there are no equivalent instructions that use B rather than A. * The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust accumulator B. * The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and CBA) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. 3.2.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can also be used as a counter or as a temporary storage register. 3.2.3 Index Register Y (IY) The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most instructions using the IY register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented. Refer to 3.4 Opcodes and Operands for further information. 3.2.4 Stack Pointer (SP) The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system. Normally, the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that grows downward from high memory to low memory. Each time a new byte is pushed onto the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. Figure 3-2 is a summary of SP operations. When a subroutine is called by a jump-to-subroutine (JSR) or branch-to- subroutine (BSR) instruction, the address of the instruction after the JSR or BSR is automatically pushed onto the stack, least significant byte first. When the subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The RTS pulls the previously stacked return address from the stack and loads it into the program counter. Execution then continues at this recovered return address. When an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. MC68HC711D3 Data Sheet, Rev. 2.1 34 Freescale Semiconductor CPU Registers JSR, JUMP TO SUBROUTINE MAIN PROGRAM $9D = JSR PC DIRECT RTN dd NEXT MAIN INSTR MAIN PROGRAM $AD = JSR ff RTN NEXT MAIN INSTR MAIN PROGRAM $18 = PRE $AD = JSR ff RTN NEXT MAIN INSTR MAIN PROGRAM $BD = JSR hh ll RTN NEXT MAIN INSTR X + ff NEXT INSTRUCTION MAIN PROGRAM $18 = PRE $6E = JMP ff INDXD,Y RTNL RTNH X + ff NEXT INSTRUCTION MAIN PROGRAM $7E = JMP hh RTNL RTNH ll EXTND INDXD,X PC SP-2 SP-1 SP STACK RTNL RTNH JMP, JUMP MAIN PROGRAM $6E = JMP ff RTI, RETURN FROM INTERRUPT INTERRUPT PROGRAM $3B = RTI PC STACK SP SP+1 SP+2 SP+3 CONDITION CODE ACMLTR B PC INDXD,X ACMLTR A SP+4 INDEX REGISTER (XH) SP+5 INDEX REGISTER (XL) SP+6 INDEX REGISTER (YH) SP+7 INDEX REGISTER (YL) RTNL SP+8 SP+9 RTNH PC INDXD,Y PC EXTEND PC BSR, BRANCH TO SUBROUTINE MAIN PROGRAM PC $8D = BSR rr RTN NEXT MAIN INSTR STACK SP-2 SP-1 SP RTS, RETURN FROM SUBROUTINE SUBROUTINE PC $39 = RTS STACK SP SP+1 SP+2 PC SWI, SOFTWARE INTERRUPT MAIN PROGRAM PC RTN $3F = SWI SP-9 SP-8 SP-7 SP-6 hh ll STACK LEGEND: NEXT INSTRUCTION CONDITION CODE ACMLTR B ACMLTR A SP-5 INDEX REGISTER (XH) WAI, WAIT FOR INTERRUPT MAIN PROGRAM PC RTN $3E = WAI SP-4 INDEX REGISTER (XL) SP-3 INDEX REGISTER (YH) SP-2 INDEX REGISTER (YL) RTNL SP-1 SP RTNH RTN Address of next instruction in main program to be executed upon return from subroutine RTNH Most significant byte of return address RTNL Least significant byte of return address Shaded cells show stack pointer position after operation is complete. dd 8-bit direct address ($0000-$00FF) (high byte assumed to be $00). ff 8-bit positive offset $00 (0) to $FF (256) is added to index. hh High-order byte of 16-bit extended address. ll Low-order byte of 16-bit extended address. rr Signed-relative offset $80 (-128) to $7F (+127) (offset relative to the address following the machine code offset byte). Figure 3-2. Stacking Operations MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 35 Central Processor Unit (CPU) At the end of the interrupt service routine, a return-from interrupt (RTI) instruction is executed. The RTI instruction causes the saved registers to be pulled off the stack in reverse order. Program execution resumes at the return address. Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often used to preserve program context. For example, pushing accumulator A onto the stack when entering a subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. 3.2.5 Program Counter (PC) The program counter, a 16-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. See Table 3-1. Table 3-1. Reset Vector Comparison Mode Normal Test or boot POR or RESET Pin $FFFE, $FFFF $BFFE, $BFFF Clock Monitor $FFFC, $FFFD $BFFC, $FFFD COP Watchdog $FFFA, $FFFB $BFFA, $FFFB 3.2.6 Condition Code Register (CCR) This 8-bit register contains: * Five condition code indicators (C, V, Z, N, and H) * Two interrupt masking bits (IRQ and XIRQ) * One stop disable bit (S) In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions do not affect the condition codes. Refer to Table 3-2, which shows what condition codes are affected by a particular instruction. 3.2.6.1 Carry/Borrow (C) The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.2.6.2 Overflow (V) The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared. 3.2.6.3 Zero (Z) The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags. For these operations, only = and conditions can be determined. MC68HC711D3 Data Sheet, Rev. 2.1 36 Freescale Semiconductor Data Types 3.2.6.4 Negative (N) The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB) is a 1. A quick way to test whether the contents of a memory location has the MSB set is to load it into an accumulator and then check the status of the N bit. 3.2.6.5 I-Interrupt Mask (I) The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending, but the operation of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is set by default and can be cleared only by a software instruction. When an interrupt is recognized, the I bit is set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, a return-from-interrupt instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. Normally, the I bit is 0 after a return from interrupt is executed. Although the I bit can be cleared within an interrupt service routine, "nesting" interrupts in this way should be done only when there is a clear understanding of latency and of the arbitration mechanism. Refer to Chapter 4 Resets, Interrupts, and Low-Power Modes. 3.2.6.6 Half Carry (H) The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is used during BCD operations. 3.2.6.7 X-Interrupt Mask (X) The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default and must be cleared by a software instruction. When an XIRQ interrupt is recognized, the X and I bits are set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is normally executed, causing the registers to be restored to the values that were present before the interrupt occurred. The X interrupt mask bit is set only by hardware (RESET or XIRQ acknowledge). X is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from the stack has been cleared). There is no hardware action for clearing X. 3.2.6.8 STOP Disable (S) Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a low-power stop condition. If the STOP instruction is encountered by the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, and processing continues to the next instruction. S is set by reset; STOP is disabled by default. 3.3 Data Types The M68HC11 CPU supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 37 Central Processor Unit (CPU) A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. 3.4 Opcodes and Operands The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. A 4-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. As its name implies, the additional byte precedes the opcode. A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. The operands contain information the CPU needs for executing the instruction. Complete instructions can be from one to five bytes long. 3.5 Addressing Modes Six addressing modes can be used to access memory: 1. Immediate 2. Direct 3. Extended 4. Indexed 5. Inherent 6. Relative These modes are detailed in the following paragraphs. All modes except inherent mode use an effective address. The effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed. The effective address can be specified within an instruction, or it can be calculated. 3.5.1 Immediate In the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. There are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction. 3.5.2 Direct In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00-$FF are thus accessed directly, using 2-byte instructions. Execution time is reduced by eliminating the additional memory access required for the high-order address byte. In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. MC68HC711D3 Data Sheet, Rev. 2.1 38 Freescale Semiconductor Instruction Set 3.5.3 Extended In the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required). One or two bytes are needed for the opcode and two for the effective address. 3.5.4 Indexed In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (IX or IY). The sum is the effective address. This addressing mode allows referencing any memory location in the 64-Kbyte address space. These are 2- to 5-byte instructions, depending on whether a prebyte is required. 3.5.5 Inherent In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. These are 1- or 2-byte instructions. 3.5.6 Relative The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte instructions. 3.6 Instruction Set Refer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Table 3-2. Instruction Set (Sheet 1 of 8) Mnemonic ABA ABX ABY ADCA (opr) Operation Add Accumulators Add B to X Add B to Y Add with Carry to A Description A+BA IX + (00 : B) IX IY + (00 : B) IY A+M+CA A A A A A B B B B B A A A A A Addressing Mode INH INH INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y 18 Opcode 1B 3A 3A 89 99 B9 A9 A9 C9 D9 F9 E9 E9 8B 9B BB AB AB ii dd hh ff ff ii dd hh ff ff ii dd hh ff ff Instruction Operand -- -- -- Cycles 2 3 4 2 3 4 4 5 2 3 4 4 5 2 3 4 4 5 S -- -- -- -- X -- -- -- -- Condition Codes H -- -- I -- -- -- -- N -- -- Z -- -- V -- -- C -- -- ll 18 ADCB (opr) Add with Carry to B B+M+CB -- -- -- ll 18 ADDA (opr) Add Memory to A A+MA -- -- -- ll 18 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 39 Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet 2 of 8) Mnemonic ADDB (opr) Operation Add Memory to B Description B+MB B B B B B Addressing Mode IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y A C b7 b0 0 Instruction Opcode CB DB FB EB EB C3 D3 F3 E3 E3 84 94 B4 A4 A4 C4 D4 F4 E4 E4 78 68 68 48 Operand ii dd hh ff ff jj dd hh ff ff ii dd hh ff ff ii dd hh ff ff hh ff ff Cycles 2 3 4 4 5 4 5 6 6 7 2 3 4 4 5 2 3 4 4 5 6 6 7 2 S -- X -- Condition Codes H I -- N Z V C ll 18 ADDD (opr) Add 16-Bit to D D + (M : M + 1) D kk ll -- -- -- -- 18 ANDA (opr) AND A with Memory A*MA -- -- -- -- 0 -- ll 18 ANDB (opr) AND B with Memory B*MB -- -- -- -- 0 -- ll 18 ASL (opr) Arithmetic Shift Left C b7 b0 ll -- -- -- -- 0 18 ASLA Arithmetic Shift Left A Arithmetic Shift Left B C b7 b0 INH -- -- -- -- -- ASLB B 0 INH 58 -- 2 -- -- -- -- ASLD Arithmetic Shift Left D C b7 A b0 b7 B b0 INH 0 05 -- 3 -- -- -- -- ASR Arithmetic Shift Right b7 b0 C EXT IND,X IND,Y A INH 18 77 67 67 47 hh ff ff ll 6 6 7 2 -- -- -- -- ASRA Arithmetic Shift Right A b7 b0 C -- -- -- -- -- ASRB Arithmetic Shift Right B b7 b0 C B INH 57 -- 2 -- -- -- -- BCC (rel) BCLR (opr) (msk) BCS (rel) BEQ (rel) BGE (rel) BGT (rel) BHI (rel) BHS (rel) BITA (opr) Branch if Carry Clear Clear Bit(s) ?C=0 M * (mm) M REL DIR IND,X IND,Y REL REL REL REL REL REL A A A A A IMM DIR EXT IND,X IND,Y 24 15 1D 1D 25 27 2C 2E 22 24 85 95 B5 A5 A5 rr dd ff ff rr rr rr rr rr rr ii dd hh ff ff mm mm mm 3 6 7 8 3 3 3 3 3 3 2 3 4 4 5 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- 18 Branch if Carry Set Branch if = Zero Branch if Zero Branch if > Zero Branch if Higher Branch if Higher or Same Bit(s) Test A with Memory ?C=1 ?Z=1 ?NV=0 ? Z + (N V) = 0 ?C+Z=0 ?C=0 A*M -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- ll 18 MC68HC711D3 Data Sheet, Rev. 2.1 40 Freescale Semiconductor Instruction Set Table 3-2. Instruction Set (Sheet 3 of 8) Mnemonic BITB (opr) Operation Bit(s) Test B with Memory Description B*M B B B B B Addressing Mode IMM DIR EXT IND,X IND,Y REL REL REL REL REL REL REL REL DIR IND,X IND,Y Opcode C5 D5 F5 E5 E5 2F 25 23 2D 2B 26 2A 20 13 1F 1F Instruction Operand ii dd hh ff ff rr rr rr rr rr rr rr rr dd rr ff rr ff rr rr dd rr ff rr ff rr dd ff ff rr rr rr -- -- -- hh ff ff ll mm mm mm mm mm mm 6 7 8 6 3 3 2 2 2 6 6 7 2 2 2 2 3 4 4 5 2 3 4 4 5 6 6 7 -- -- -- -- 0 -- mm mm mm 3 6 7 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Cycles 2 3 4 4 5 3 3 3 3 3 3 3 3 6 7 8 S -- X -- Condition Codes H -- I -- N Z V 0 C -- ll 18 BLE (rel) BLO (rel) BLS (rel) BLT (rel) BMI (rel) BNE (rel) BPL (rel) BRA (rel) BRCLR(opr) (msk) (rel) Branch if Zero Branch if Lower Branch if Lower or Same Branch if < Zero Branch if Minus Branch if not = Zero Branch if Plus Branch Always Branch if Bit(s) Clear ? Z + (N V) = 1 ?C=1 ?C+Z=1 ?NV=1 ?N=1 ?Z=0 ?N=0 ?1=1 ? M * mm = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 BRN (rel) BRSET(opr) (msk) (rel) Branch Never Branch if Bit(s) Set ?1=0 ? (M) * mm = 0 REL DIR IND,X IND,Y 21 12 1E 1E 18 BSET (opr) (msk) BSR (rel) BVC (rel) BVS (rel) CBA CLC CLI CLR (opr) Set Bit(s) M + mm M DIR IND,X IND,Y REL REL REL INH INH INH EXT IND,X IND,Y A B INH INH INH A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y 18 14 1C 1C 8D 28 29 11 0C 0E 7F 6F 6F 4F 5F 0A 81 91 B1 A1 A1 C1 D1 F1 E1 E1 73 63 63 Branch to Subroutine Branch if Overflow Clear Branch if Overflow Set Compare A to B Clear Carry Bit Clear Interrupt Mask Clear Memory Byte Clear Accumulator A Clear Accumulator B Clear Overflow Flag Compare A to Memory See Figure 3-2 ?V=0 ?V=1 A-B 0C 0I 0M -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- 0 -- -- -- -- -- 1 -- -- -- -- -- 0 -- -- -- 0 -- 0 18 CLRA CLRB CLV CMPA (opr) 0A 0B 0V A-M -- -- -- ii dd hh ff ff ii dd hh ff ff hh ff ff -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- 1 1 -- 0 0 0 0 0 -- ll 18 CMPB (opr) Compare B to Memory B-M -- -- -- -- ll 18 COM (opr) Ones Complement Memory Byte $FF - M M ll -- -- -- -- 0 1 18 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 41 Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet 4 of 8) Mnemonic COMA Operation Ones Complement A Ones Complement B Compare D to Memory 16-Bit Description $FF - A A A Addressing Mode INH Opcode 43 Instruction Operand -- Cycles 2 S -- X -- Condition Codes H -- I -- N Z V 0 C 1 COMB $FF - B B B INH 53 -- 2 -- -- -- -- 0 1 CPD (opr) D-M:M +1 IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH EXT IND,X IND,Y A INH 1A 1A 1A 1A CD 83 93 B3 A3 A3 8C 9C BC AC AC 8C 9C BC AC AC 19 7A 6A 6A 4A jj dd hh ff ff jj dd hh ff ff jj dd hh ff ff kk ll 5 6 7 7 7 4 5 6 6 7 5 6 7 7 7 2 6 6 7 2 -- -- -- -- CPX (opr) Compare X to Memory 16-Bit IX - M : M + 1 kk ll -- -- -- -- CD 18 18 18 1A 18 CPY (opr) Compare Y to Memory 16-Bit IY - M : M + 1 kk ll -- -- -- -- DAA DEC (opr) Decimal Adjust A Decrement Memory Byte Decrement Accumulator A Decrement Accumulator B Decrement Stack Pointer Decrement Index Register X Decrement Index Register Y Exclusive OR A with Memory Adjust Sum to BCD M-1M -- hh ff ff ll -- -- -- -- -- -- -- -- -- 18 DECA A-1A -- -- -- -- -- -- DECB B-1B B INH 5A -- 2 -- -- -- -- -- DES DEX SP - 1 SP IX - 1 IX INH INH 34 09 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEY IY - 1 IY INH 18 09 -- 4 -- -- -- -- -- -- -- EORA (opr) AMA A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH EXT IND,X IND,Y 18 88 98 B8 A8 A8 C8 D8 F8 E8 E8 03 02 7C 6C 6C 4C ii dd hh ff ff ii dd hh ff ff ll 2 3 4 4 5 2 3 4 4 5 41 41 6 6 7 2 -- -- -- -- 0 -- EORB (opr) Exclusive OR B with Memory BMB -- -- -- -- 0 -- ll 18 FDIV IDIV INC (opr) Fractional Divide 16 by 16 Integer Divide 16 by 16 Increment Memory Byte Increment Accumulator A Increment Accumulator B Increment Stack Pointer D / IX IX; r D D / IX IX; r D M+1M -- -- hh ff ff ll -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 18 INCA A+1A A INH -- -- -- -- -- -- INCB B+1B B INH 5C -- 2 -- -- -- -- -- INS SP + 1 SP INH 31 -- 3 -- -- -- -- -- -- -- -- MC68HC711D3 Data Sheet, Rev. 2.1 42 Freescale Semiconductor Instruction Set Table 3-2. Instruction Set (Sheet 5 of 8) Mnemonic INX Operation Increment Index Register X Increment Index Register Y Jump Description IX + 1 IX Addressing Mode INH Opcode 08 Instruction Operand -- Cycles 3 S -- X -- Condition Codes H -- I -- N -- Z V -- C -- INY IY + 1 IY INH 18 08 -- 4 -- -- -- -- -- -- -- JMP (opr) See Figure 3-2 EXT IND,X IND,Y DIR EXT IND,X IND,Y A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y A INH 18 7E 6E 6E 9D BD AD AD 86 96 B6 A6 A6 C6 D6 F6 E6 E6 CC DC FC EC EC 8E 9E BE AE AE CE DE FE EE EE CE DE FE EE EE 78 68 68 48 hh ff ff dd hh ff ff ii dd hh ff ff ii dd hh ff ff jj dd hh ff ff jj dd hh ff ff jj dd hh ff ff jj dd hh ff ff hh ff ff ll 3 3 4 5 6 6 7 2 3 4 4 5 2 3 4 4 5 3 4 5 5 6 3 4 5 5 6 3 4 5 5 6 4 5 6 6 6 6 6 7 2 -- -- -- -- -- -- -- -- JSR (opr) Jump to Subroutine See Figure 3-2 -- -- -- -- -- -- -- -- ll 18 LDAA (opr) Load Accumulator A MA -- -- -- -- 0 -- ll 18 LDAB (opr) Load Accumulator B MB -- -- -- -- 0 -- ll 18 LDD (opr) Load Double Accumulator D M A,M + 1 B kk ll -- -- -- -- 0 -- 18 LDS (opr) Load Stack Pointer M : M + 1 SP kk ll -- -- -- -- 0 -- 18 LDX (opr) Load Index Register X M : M + 1 IX kk ll -- -- -- -- 0 -- CD 18 18 18 1A 18 LDY (opr) Load Index Register Y M : M + 1 IY kk ll -- -- -- -- 0 -- LSL (opr) Logical Shift Left C b7 b0 ll -- -- -- -- 0 18 LSLA Logical Shift Left A C b7 b0 -- -- -- -- -- 0 LSLB Logical Shift Left B C b7 b0 B 0 INH 58 -- 2 -- -- -- -- LSLD Logical Shift Left Double C b7 A b0 b7 B b0 INH 0 05 -- 3 -- -- -- -- LSR (opr) Logical Shift Right Logical Shift Right A Logical Shift Right B 0 b7 b0 C EXT IND,X IND,Y A INH 18 74 64 64 44 hh ff ff ll 6 6 7 2 -- -- -- -- 0 LSRA -- -- -- -- -- 0 0 b7 b0 C LSRB B 0 b7 b0 C INH 54 -- 2 -- -- -- -- 0 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 43 Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet 6 of 8) Mnemonic LSRD Operation Logical Shift Right Double Multiply 8 by 8 Two's Complement Memory Byte Two's Complement A Two's Complement B No operation OR Accumulator A (Inclusive) Description Addressing Mode INH 0 b7 A b0 b7 B b0 C Instruction Opcode 04 Operand -- Cycles 3 S -- X -- Condition Codes H -- I -- N 0 Z V C MUL NEG (opr) ABD 0-MM INH EXT IND,X IND,Y A INH 3D 70 60 60 40 hh ff ff -- ll 10 6 6 7 2 -- -- -- -- -- -- -- -- -- -- -- 18 NEGA 0-AA -- -- -- -- -- NEGB 0-BB B INH 50 -- 2 -- -- -- -- NOP ORAA (opr) No Operation A+MA A A A A A B B B B B INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH INH 01 8A 9A BA AA AA CA DA FA EA EA 36 37 3C ii dd hh ff ff ii dd hh ff ff -- 2 2 3 4 4 5 2 3 4 4 5 3 3 4 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- ll 18 ORAB (opr) OR Accumulator B (Inclusive) B+MB -- -- -- -- 0 -- ll 18 PSHA PSHB PSHX Push A onto Stack Push B onto Stack Push X onto Stack (Lo First) Push Y onto Stack (Lo First) Pull A from Stack Pull B from Stack Pull X From Stack (Hi First) Pull Y from Stack (Hi First) Rotate Left A Stk,SP = SP - 1 A B Stk,SP = SP - 1 B IX Stk,SP = SP - 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSHY IY Stk,SP = SP - 2 INH 18 3C -- 5 -- -- -- -- -- -- -- -- PULA PULB PULX SP = SP + 1, A Stk A SP = SP + 1, B Stk B SP = SP + 2, IX Stk INH INH INH 32 33 38 -- -- -- 4 4 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PULY SP = SP + 2, IY Stk INH 18 38 -- 6 -- -- -- -- -- -- -- -- ROL (opr) C b7 b0 EXT IND,X IND,Y A INH 18 79 69 69 49 hh ff ff ll 6 6 7 2 -- -- -- -- ROLA Rotate Left A C b7 b0 -- -- -- -- -- ROLB Rotate Left B C b7 b0 B INH 59 -- 2 -- -- -- -- ROR (opr) Rotate Right b7 b0 C EXT IND,X IND,Y A INH 18 76 66 66 46 hh ff ff ll 6 6 7 2 -- -- -- -- RORA Rotate Right A b7 b0 C -- -- -- -- -- RORB Rotate Right B b7 b0 C B INH 56 -- 2 -- -- -- -- RTI Return from Interrupt See Figure 3-2 INH 3B -- 12 MC68HC711D3 Data Sheet, Rev. 2.1 44 Freescale Semiconductor Instruction Set Table 3-2. Instruction Set (Sheet 7 of 8) Mnemonic RTS SBA SBCA (opr) Operation Return from Subroutine Subtract B from A Subtract with Carry from A Description See Figure 3-2 A-BA A-M-CA A A A A A B B B B B Addressing Mode INH INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH INH A A A A B B B B DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y INH DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y A A A A A A A A A A IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH INH Opcode 39 10 82 92 B2 A2 A2 C2 D2 F2 E2 E2 0D 0F 0B 97 B7 A7 A7 D7 F7 E7 E7 DD FD ED ED CF 9F BF AF AF DF FF EF EF DF FF EF EF 80 90 B0 A0 A0 C0 D0 F0 E0 E0 83 93 B3 A3 A3 3F 16 06 dd hh ff ff dd hh ff ff dd hh ff ff ii dd hh ff ff ii dd hh ff ff jj dd hh ff ff dd hh ff ff dd hh ff ff dd hh ff ff ii dd hh ff ff ii dd hh ff ff Instruction Operand -- -- Cycles 5 2 2 3 4 4 5 2 3 4 4 5 2 2 2 3 4 4 5 3 4 4 5 4 5 5 6 2 4 5 5 6 4 5 5 6 5 6 6 6 2 3 4 4 5 2 3 4 4 5 4 5 6 6 7 14 2 2 S -- -- -- X -- -- -- Condition Codes H -- -- -- I -- -- -- N -- Z -- V -- C -- ll 18 SBCB (opr) Subtract with Carry from B B-M-CB -- -- -- -- ll 18 SEC SEI SEV STAA (opr) Set Carry Set Interrupt Mask Set Overflow Flag Store Accumulator A Store Accumulator B Store Accumulator D Stop Internal Clocks Store Stack Pointer 1C 1I 1V AM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- 1 0 1 -- -- -- ll 18 STAB (opr) BM -- -- -- -- 0 -- ll 18 STD (opr) A M, B M + 1 -- -- -- -- 0 -- ll 18 STOP STS (opr) -- SP M : M + 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- ll 18 STX (opr) Store Index Register X IX M : M + 1 -- -- -- -- 0 -- ll CD 18 18 1A 18 STY (opr) Store Index Register Y IY M : M + 1 -- -- -- -- 0 -- ll SUBA (opr) Subtract Memory from A A-MA -- -- -- -- ll 18 SUBB (opr) Subtract Memory from B B-MB -- -- -- -- ll 18 SUBD (opr) Subtract Memory from D D-M:M+1D kk ll -- -- -- -- 18 SWI TAB TAP Software Interrupt Transfer A to B Transfer A to CC Register See Figure 3-2 AB A CCR -- -- -- -- -- -- -- -- -- 1 -- -- -- -- 0 -- -- MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 45 Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet 8 of 8) Mnemonic TBA TEST TPA TST (opr) Operation Transfer B to A TEST (Only in Test Modes) Transfer CC Register to A Test for Zero or Minus Test A for Zero or Minus Test B for Zero or Minus Transfer Stack Pointer to X Transfer Stack Pointer to Y Transfer X to Stack Pointer Transfer Y to Stack Pointer Wait for Interrupt Exchange D with X Exchange D with Y Description BA Address Bus Counts CCR A M-0 Addressing Mode INH INH INH EXT IND,X IND,Y A B INH INH INH INH INH INH INH INH INH 18 18 18 Opcode 17 00 07 7D 6D 6D 4D 5D 30 30 35 35 3E 8F 8F hh ff ff Instruction Operand -- -- -- ll Cycles 2 * 2 6 6 7 2 2 3 4 3 4 ** 3 4 S -- -- -- -- X -- -- -- -- Condition Codes H -- -- -- -- I -- -- -- -- N -- -- Z -- -- V 0 -- -- 0 C -- -- -- 0 18 TSTA TSTB TSX TSY TXS TYS WAI XGDX XGDY A-0 B-0 SP + 1 IX SP + 1 IY IX - 1 SP IY - 1 SP Stack Regs & WAIT IX D, D IX IY D, D IY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- -- Cycle * ** Infinity or until reset occurs 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). Operands dd = 8-bit direct address ($0000-$00FF) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index) hh = High-order byte of 16-bit extended address ii = One byte of immediate data jj = High-order byte of 16-bit immediate data kk = Low-order byte of 16-bit immediate data ll = Low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = Signed relative offset $80 (-128) to $7F (+127) (offset relative to address following machine code offset byte) Operators () Contents of register shown inside parentheses Is transferred to Is pulled from stack Is pushed onto stack * Boolean AND + Arithmetic addition symbol except where used as inclusive-OR symbol in Boolean formula Exclusive-OR Multiply : Concatenation - Arithmetic subtraction symbol or negation symbol (two's complement) Condition Codes -- Bit not changed 0 Bit always cleared 1 Bit always set Bit cleared or set, depending on operation Bit can be cleared, cannot become set MC68HC711D3 Data Sheet, Rev. 2.1 46 Freescale Semiconductor Chapter 4 Resets, Interrupts, and Low-Power Modes 4.1 Introduction This section describes the internal and external resets and interrupts of the MC68HC711D3 and its two low power-consumption modes. 4.2 Resets The microcontroller unit (MCU) can be reset in any of these four ways: 1. An active-low input to the RESET pin 2. A power-on reset (POR) function 3. A clock monitor failure 4. A computer operating properly (COP) watchdog timer timeout The RESET input consists mainly of a Schmitt trigger that senses the RESET line logic level. 4.2.1 RESET Pin To request an external reset, the RESET pin must be held low for at least eight E-clock cycles, or for one E-clock cycle if no distinction is needed between internal and external resets. 4.2.2 Power-On Reset (POR) Power-on reset occurs when a positive transition is detected on VDD. This reset is used strictly for power turn on conditions and should not be used to detect any drop in the power supply voltage. If the external RESET pin is low at the end of the power-on delay time, the processor remains in the reset condition until RESET goes high. 4.2.3 Computer Operating Properly (COP) Reset The MCU contains a watchdog timer that automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, a reset is generated, which drives the RESET pin low to reset the MCU and the external system. In the MC68HC711D3, the COP reset function is enabled out of reset in normal modes. If the user does not want the COP enabled, he must write a 1 to the NOCOP bit of the configuration control register (CONFIG) after reset. This bit is writable only once after reset in normal modes (see 2.3.3 Configuration Control Register for more information). Protected control bits (CR1 and CR0) in the configuration options register (OPTION) allow the user to select one of the four COP timeout rates. Table 4-1 shows the relationship between CR1 and CR0 and the COP timeout period for various system clock frequencies. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 47 Resets, Interrupts, and Low-Power Modes The sequence for resetting the watchdog timer is: 1. Write $55 to the COP reset register (COPRST) to arm the COP timer clearing mechanism. 2. Write $AA to the COPRST register to clear the COP timer Both writes must occur in this sequence prior to the timeout, but any number of instructions can be executed between the two writes. Table 4-1. COP Time Out Periods E / 215 CR0 CR1 Divided By 0 0 1 1 0 1 0 1 1 4 16 64 E= XTAL = 223 Time Out -0/+15.6 ms 15.625 ms 62.5 ms 250 ms 1 sec 2.1 MHz XTAL = 8.0 MHz Time Out -0/+16.4 ms 16.384 ms 65.536 ms 262.14 ms 1.049 sec 2.0 MHz XTAL = 4.9152 MHz Time Out -0/+26.7 ms 26.667 ms 106.67 ms 426.67 ms 1.707 sec 1.2288 MHz XTAL = 4.0 MHz Time Out -0/+32.8 ms 32.768 ms 131.07 ms 524.29 ms 2.1 sec 1.0 MHz XTAL = 3.6864 MHz Time Out -0/+35.6 ms 35.556 ms 142.22 ms 568.89 ms 2.276 ms 921.6 kHz Address: Read: Write: Reset: $003A Bit 7 Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0 Figure 4-1. Arm/Reset COP Timer Circuitry Register (COPRST) 4.2.4 Clock Monitor Reset The MCU contains a clock monitor circuit that measures the E-clock frequency. If the E-clock input rate is above approximately 200 kHz, then the clock monitor does not generate an MCU reset. If the E-clock signal is lost or its frequency falls below 10 kHz, then an MCU reset can be generated, and the RESET pin is driven low to reset the external system. 4.2.5 System Configuration Options Register The system configuration options register (OPTION) is a special-purpose register with several time-protected bits. OPTION is used during initialization to configure internal system options. Bits 5, 4, 2, 1, and 0 can be written only once during the first 64 E-clock cycles after reset in normal modes (where the HPRIO register bit (SMOD) is cleared). In special modes (where SMOD = 1), the bits can be written at any time. Bit 3 can be written at anytime. MC68HC711D3 Data Sheet, Rev. 2.1 48 Freescale Semiconductor Interrupts Address: Read: Write: Reset: $0039 Bit 7 0 0 6 0 0 5 IRQE 0 4 DLY 1 3 CME 0 2 0 0 1 CR1 0 Bit 0 CR0 0 Figure 4-2. System Configuration Options Register (OPTION) Bits 7, 6, and 2 -- Not implemented Always read 0. IRQE -- IRQ Edge/Level Sensitivity Select This bit can be written only once during the first 64 E-clock cycles after reset in normal modes. 1 = IRQ is configured to respond only to falling edges. 0 = IRQ is configured for low-level wired-OR operation. DLY -- Stop Mode Exit Turnon Delay This bit is set during reset and can be written only once during the first 64 E-clock cycles after reset in normal modes. If an external clock source rather than a crystal is used, the stabilization delay can be inhibited because the clock source is assumed to be stable. 1 = A stabilization delay of 4064 E-clock cycles is imposed before processing resumes after a stop mode wakeup. 0 = No stabilization delay is imposed after story recovery. CME -- Clock Monitor Enable 1 = Clock monitor circuit is enabled. 0 = Clock monitor circuit is disabled. CR1 and CR0 -- COP Timer Rate Selects The COP system is driven by a constant frequency of E / 215. These two bits specify an additional divide-by value to arrive at the COP timeout rate. These bits are cleared during reset and can be written only once during the first 64 E-clock cycles after reset in normal modes. The value of these bits is: CR1 0 0 1 1 CR0 0 1 0 1 E / 215 Divided By 1 4 16 64 4.3 Interrupts Excluding reset-type interrupts, there are 17 hardware interrupts and one software interrupt that can be generated from all the possible sources. These interrupts can be divided into two categories: maskable and non-maskable. Fifteen of the interrupts can be masked using the I bit of the condition code register (CCR). All the on-chip (hardware) interrupts are individually maskable by local control bits. The software interrupt is non-maskable. The external input to the XIRQ pin is considered a non-maskable interrupt because it cannot be masked by software once it is enabled. However, it is masked during reset and upon receipt of an interrupt at the XIRQ pin. Illegal opcode is also a non-maskable interrupt. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 49 Resets, Interrupts, and Low-Power Modes Table 4-2 provides a list of the interrupts with a vector location in memory for each, as well as the actual condition code and control bits that mask each interrupt. Figure 4-3 shows the interrupt stacking order. Table 4-2. Interrupt and Reset Vector Assignments Vector Address $FFC0, $FFC1 $FFD4, $FFD5 Reserved SCI serial system: * SCI transmit complete * SCI transmit data register empty * SCI idle line detect * SCI receiver overrun * SCI receive data register full SPI serial transfer complete Pulse accumulator input edge Pulse accumulator overflow Timer overflow Timer input capture 4/output compare 5 Timer output compare 4 Timer output compare 3 Timer output compare 2 Timer output compare 1 Timer input capture 3 Timer input capture 2 Timer input capture 1 Real time interrupt IRQ (external pin) XIRQ pin (pseudo non-maskable) Software interrupt Illegal opcode trap COP failure (reset) Clock monitor fail (reset) RESET Interrupt Source CCR Mask -- Local Mask -- $FFD6, $FFD7 I bit TCIE TIE ILIE RIE RIE SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCOP CME None $FFD8, $FFD9 $FFDA, $FFDB $FFDC, $FFDD $FFDE, $FFDF $FFE0, $FFE1 $FFE2, $FFE3 $FFE4, $FFE5 $FFE6, $FFE7 $FFE8, $FFE9 $FFEA, $FFEB $FFEC, $FFED $FFEE, $FFEF $FFF0, $FFF1 $FFF2, $FFF3 $FFF4, $FFF5 $FFF6, $FFF7 $FFF8, $FFF9 $FFFA, $FFFB $FFFC, $FFFD $FFFE, $FFFF I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit X bit None None None None None MC68HC711D3 Data Sheet, Rev. 2.1 50 Freescale Semiconductor Interrupts STACK SP SP - 1 SP - 2 SP - 3 SP - 4 SP - 5 SP - 6 SP - 7 SP - 8 SP - 9 PCL PCH IYL IYH -- SP BEFORE INTERRUPT IXL IXH ACCA ACCB CCR -- SP AFTER INTERRUPT Figure 4-3. Interrupt Stacking Order 4.3.1 Software Interrupt (SWI) The SWI is executed the same as any other instruction and takes precedence over interrupts only if the other interrupts are masked (with I and X bits in the CCR set). SWI execution is similar to that of the maskable interrupts in that it sets the I bit, stacks the central processor unit (CPU) registers, etc. NOTE The SWI instruction cannot be executed as long as another interrupt is pending. However, once the SWI instruction has begun, no other interrupt can be honored until the first instruction in the SWI service routine is completed. 4.3.2 Illegal Opcode Trap Since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit has been included in the MCU. When an illegal opcode is detected, an interrupt is required to the illegal opcode vector. The illegal opcode vector should never be left uninitialized. 4.3.3 Real-Time Interrupt (RTI) The real-time interrupt (RTI) provides a programmable periodic interrupt. This interrupt is maskable by either the I bit in the CCR or the RTI enable (RTII) bit of the timer interrupt mask register 2 (TMSK2). The rate is based on the MCU E clock and is software selectable to the E / 213, E / 214, E / 215, or E / 216. See PACTL, TMSK2, and TFLG2 register descriptions in Chapter 8 Programmable Timer for control and status bit information. 4.3.4 Interrupt Mask Bits in the CCR Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable interrupts and XIRQ. After minimum system initialization, software may clear the X bit by a TAP instruction, thus enabling XIRQ interrupts. Thereafter software cannot set the X bit. So, an XIRQ interrupt is effectively a non-maskable interrupt. Since the operation of the I bit related interrupt structure has no effect on the X bit, the internal XIRQ pin remains effectively non-masked. In the interrupt priority logic, the XIRQ interrupt is a higher priority than any source that is maskable by the I bit. All I bit related interrupts operate normally with their own priority relationship. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 51 Resets, Interrupts, and Low-Power Modes When an I bit related interrupt occurs, the I bit is automatically set by hardware after stacking the CCR byte. The X bit is not affected. When an X bit related interrupt occurs, both the X and the I bit are automatically set by hardware after stacking the CCR. A return-from-interrupt (RTI) instruction restores the X and I bits to their preinterrupt request state. 4.3.5 Priority Structure Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests. However one I bit related interrupt source may be elevated to the highest I bit priority in the resolution circuit. Six interrupt sources are not masked by the I bit in the CCR and have these fixed priority relationships: 1. Reset 2. Clock monitor failure 3. COP failure 4. Illegal opcode 5. SWI 6. XIRQ SWI is actually an instruction and has highest priority, other than resets, in that once the SWI opcode is fetched, no other interrupt can be honored until the SWI vector has been fetched. Each of the previous sources is an input to the priority resolution circuit. The highest I bit masked priority input to the resolution circuit is assigned to be connected to any one of the remaining I bit related interrupt sources. This assignment is made under the software control of the HPRIO register. To avoid timing races, the HPRIO register can be written only while the I bit related interrupts are inhibited (I bit of CCR is logic 1). An interrupt that is assigned to this higher priority position is still subject to masking by any associated control bits or by the I bit in the CCR. The interrupt vector address is not affected by assigning a source to the higher priority position. Figure 4-4, Figure 4-5, and Figure 4-6 illustrate the interrupt process as it relates to normal processing. Figure 4-4 shows how the CPU begins from a reset, and how interrupt detection relates to normal opcode fetches. Figure 4-5 is an expansion of a block in Figure 4-4 and shows how interrupt priority is resolved. Figure 4-6 is an expansion of the SCI interrupt block of Figure 4-4 and shows the resolution of interrupt sources within the SCI subsystem. MC68HC711D3 Data Sheet, Rev. 2.1 52 Freescale Semiconductor Interrupts HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) LOWEST PRIORITY COP WATCHDOG TIMEOUT (WITH NOCOP = 0) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFA, $FFFB (VECTOR FETCH) SET BITS S, I, AND X RESET MCU HARDWARE 1A BEGIN INSTRUCTION SEQUENCE Y BIT X IN CCR = 1? N XIRQ PIN LOW? N Y STACK CPU REGISTERS SET BITS I AND X FETCH VECTOR $FFF4, $FFF5 2A Figure 4-4. Processing Flow Out of Reset (Sheet 1 of 2) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 53 Resets, Interrupts, and Low-Power Modes 2A Y I BIT IN CCR SET? N ANY I-BIT INTERRUPT PENDING? N FETCH OPCODE Y STACK CPU REGISTERS STACK CPU REGISTERS N ILLEGAL OPCODE? Y SET I BIT WAI Y INSTRUCTION? FETCH VECTOR $FFF8, $FFF9 N Y SWI INSTRUCTION? N SET I BIT Y FETCH VECTOR $FFF6, $FFF7 RESTORE CPU REGISTERS FROM STACK RTI INSTRUCTION? N EXECUTE THIS INSTRUCTION STACK CPU REGISTERS STACK CPU REGISTERS N INTERRUPT YET? Y SET I BIT RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE SEE Figure 4-5 1A START NEXT INSTRUCTION SEQUENCE Figure 4-4. Processing Flow Out of Reset (Sheet 2 of 2) MC68HC711D3 Data Sheet, Rev. 2.1 54 Freescale Semiconductor Interrupts BEGIN X BIT IN CCR SET ? N Y XIRQ PIN LOW ? N Y SET X BIT FETCH VECTOR $FFF4, $FFF5 HIGHEST PRIORITY INTERRUPT ? N Y FETCH VECTOR IRQ ? N Y FETCH VECTOR $FFF2, $FFF3 RTII = 1 ? N Y REAL-TIME INTERRUPT ? N Y FETCH VECTOR $FFF0, $FFF1 Y IC1I = 1 ? N TIMER IC1F ? N Y FETCH VECTOR $FFEE, $FFEF Y IC2I = 1 ? N TIMER IC2F ? N Y FETCH VECTOR $FFEC, $FFED Y IC3I = 1 ? N TIMER IC3F ? N Y FETCH VECTOR $FFEA, $FFEB Y OC1I = 1 ? N 2A TIMER OC1F ? N Y FETCH VECTOR $FFE8, $FFE9 2B Figure 4-5. Interrupt Priority Resolution (Sheet 1 of 2) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 55 Resets, Interrupts, and Low-Power Modes 2A 2B Y OC2I = 1? N Y FLAG OC2F = 1? N Y FETCH VECTOR $FFE6, $FFE7 OC3I = 1? N FLAG OC3F = 1 N Y FETCH VECTOR $FFE4, $FFE5 OC4I = 1? N Y FLAG OC4F = 1? N Y FETCH VECTOR $FFE2, $FFE3 OC5I = 1? N Y FLAG OC5F = 1? N Y FETCH VECTOR $FFE0, $FFE1 Y TOI = 1? N Y FLAG TOF = 1? N Y FETCH VECTOR $FFDE, $FFDF PAOVI = 1? N FLAG PAOVF = 1 N Y FETCH VECTOR $FFDC, $FFDD PAII = 1? N Y FLAG PAIF = 1? N Y FETCH VECTOR $FFDA, $FFDB SPIE = 1? N SCI INTERRUPT? SEE Figure 4-6 N Y FLAGS SPIF = 1? OR MODF = 1? N Y FETCH VECTOR $FFD8, $FFD9 Y FETCH VECTOR $FFD6, $FFD7 FETCH VECTOR $FFF2, $FFF3 END Figure 4-5. Interrupt Priority Resolution (Sheet 2 of 2) MC68HC711D3 Data Sheet, Rev. 2.1 56 Freescale Semiconductor Interrupts BEGIN FLAG RDRF = 1? N Y OR = 1? N Y RIE = 1? N Y RE = 1? N Y TDRE = 1? N Y TIE = 1? N Y TE = 1? N Y TC = 1? N Y TCIE = 1? N Y IDLE = 1? N Y ILIE = 1? N Y RE = 1? N Y NO VALID SCI REQUEST YES VALID SCI REQUEST Figure 4-6. Interrupt Source Resolution within SCI MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 57 Resets, Interrupts, and Low-Power Modes 4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO) Four bits of this register (PSEL3-PSEL0) are used to select one of the I bit related interrupt sources and to elevate it to the highest I bit masked position of the priority resolution circuit. In addition, four miscellaneous system control bits are included in this register. Address: Read: Write: Reset: $003C Bit 7 RBOOT 6 SMOD Note 1 5 MDA 4 IRVNE 3 PSEL3 0 2 PSEL2 1 1 PSEL1 0 Bit 0 PSEL0 1 1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the mode during initialization. Refer to Table 4-3. Figure 4-7. Highest Priority I-Bit Interrupt and Miscellaneous Register (HPRIO) RBOOT -- Read Bootstrap ROM This bit can be read at any time. It can be written only in special modes (SMOD = 1). In special bootstrap mode, it is set during reset. Reset clears it in all other modes. 1 = Bootloader ROM is enabled in the memory map at $BF00-$BFFF. 0 = Bootloader ROM is disabled and is not in the memory map. SMOD and MDA -- Special Mode Select and Mode Select A These two bits can be read at any time.These bits reflect the status of the MODA and MODB input pins at the rising edge of reset. SMOD may be written only in special modes. It cannot be written to a 1 after being cleared without an interim reset. MDA may be written at any time in special modes, but only once in normal modes. An interpretation of the values of these two bits is shown in Table 4-3. Table 4-3. Hardware Mode Select Summary Inputs Mode MODB 1 1 0 0 MODA 0 1 0 1 Single chip Expanded multiplexed Special bootstrap Special test SMOD 0 0 1 1 MDA 0 1 0 1 Latched at Reset IRVNE -- Internal Read Visibility/Not E This bit may be read at any time. It may be written once in any mode. IRVNE is set during reset in special test mode only, and cleared by reset in the other modes. 1 = Data from internal reads is driven out on the external data bus in expanded modes. 0 = Data from internal reads is not visible on the external data bus. As shown in the table, in single-chip and bootstrap modes IRVNE determines whether the E clock is driven out or forced low. 1 = E pin driven low 0 = E clock driven out of the chip MC68HC711D3 Data Sheet, Rev. 2.1 58 Freescale Semiconductor Interrupts IRVNE E Clock IRV IRVNE IRVNE Out Out Out Affects May of Reset of Reset of Reset Only be Written 0 0 0 1 On On On On Off Off Off On E IRV E IRV Once Once Once Once Mode Single chip Expanded multiplexed Bootstrap Special test NOTE To prevent bus conflicts, when using internal read visibility, the user must disable all external devices from driving the data bus during any internal access. PSEL3-PSEL0 -- Priority Selects These four bits are used to specify one I bit related interrupt source, which then becomes the highest priority I bit related interrupt source. These bits may be written only while the I bit in the CCR is set, inhibiting I bit related interrupts. An interpretation of the value of these bits is shown in Table 4-4. During reset, PSEL3-PSEL0 are initialized to 0101, which corresponds to reserved (default to IRQ). IRQ becomes the highest priority I bit related interrupt source. Table 4-4. Highest Priority Interrupt Selection PSEL3-PSEL0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI serial system Reserved (default to IRQ) IRQ (external pin) Real-time interrupt Timer input capture 1 Timer input capture 2 Timer input capture 3 Timer output compare 1 Timer output compare 2 Timer output compare 3 Timer output compare 4 Timer input capture 4/output compare 5 Interrupt Source Promoted MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 59 Resets, Interrupts, and Low-Power Modes 4.4 Low-Power Operation The M68HC11 Family of microcontroller units (MCU) has two programmable low power-consumption modes: stop and wait. In the wait mode, the on-chip oscillator remains active. In the stop mode, the oscillator is stopped. This subsection describes these two low power-consumption modes. 4.4.1 Stop Mode The STOP instruction places the MCU in its lowest power-consumption mode, provided the S bit in the CCR is cleared. In this mode, all clocks are stopped, thereby halting all internal processing. To exit the stop mode, a low level must be applied to either the IRQ, XIRQ, or RESET pin. An external interrupt used at IRQ is only effective if the I bit in the CCR is cleared. An external interrupt applied at the XIRQ input is effective, regardless of the setting of the X bit of the CCR. However, the actual recovery sequence differs, depending on the X bit setting. If the X bit is cleared, the MCU starts with the stacking sequence leading to the normal service of the XIRQ request. If the X bit is set, the processing always continues with the instruction immediately following the STOP instruction. A low input to the RESET pin always results in an exit from the stop mode, and the start of MCU operations is determined by the reset vector. The CPU will not exit stop mode correctly when interrupted by IRQ or XIRQ if the instruction preceding STOP is a column 4 or 5 accumulator inherent (opcodes $4X and $5X) instruction, such as NEGA, NEGB, COMA, COMB, etc. These single-byte, two-cycle instructions must be followed by an NOP, then the STOP command. If reset is used to exit stop mode, the CPU will respond properly. A restart delay is required if the internal oscillator is being used. The delay allows the oscillator to stabilize when exiting the stop mode. If a stable external oscillator is being used, the delay (DLY) bit in the OPTION register can be cleared to bypass the delay. If the DLY bit is clear, the RESET pin would not normally be used to exit the stop mode. The reset sequence sets the DLY bit, and the restart delay would be reimposed. 4.4.2 Wait Mode The wait (WAI) instruction places the MCU in a low power-consumption mode. The wait mode consumes more power than the stop mode since the oscillator is kept running. Upon execution of the WAI instruction, the machine state is stacked and program execution stops. The wait state can be exited only by an unmasked interrupt or RESET. If the I bit of the CCR is set and the COP is disabled, the timer system is turned off by WAI to further reduce power consumption. The amount of power savings is application dependent. It also depends upon the circuitry connected to the MCU pins, and upon subsystems such as the timer, serial peripheral interface (SPI), or serial communications interface (SCI) that were or were not active when the wait mode was entered. MC68HC711D3 Data Sheet, Rev. 2.1 60 Freescale Semiconductor Chapter 5 Input/Output (I/O) Ports 5.1 Introduction The MC68HC711D3 has four 8-bit input/output (I/O) ports; A, B, C, and D. In the 40-pin version, port A bits 4 and 6 are not bonded. Port functions are controlled by the particular mode of operation selected, as shown in Table 1-1. Port Signal Functions. In the single-chip and bootstrap modes, all the ports are configured as parallel input/output (I/O) data ports. In expanded multiplexed and test modes, ports B, C, and lines D6 (AS) and D7 (R/W) are configured as a memory expansion bus, with: * Port B as the high-order address bus * Port C as the multiplexed address and data bus * AS as the demultiplexing signal * R/W as data bus direction control The remaining ports are unaffected by mode changes. * Ports A and D can be used as general-purpose I/O ports, though each has an alternate function. * Port A bits handle the timer functions. * Port D handles serial peripheral interface (SPI) and serial communications interface (SCI) functions in addition to its bus direction control functions. 5.2 Port A Port A shares functions with the timer system and has: * Three input only pins * Three output only pins * Two bidirectional I/O pins Pins PA6 and PA4 are not bonded in the 40-pin dual in-line package (DIP), and their OC output functions are unavailable, but their software interrupts are available. Address: Read: Write: Reset: Alt. Func.: And/Or: $0000 Bit 7 PA7 Hi-Z PAI OC1 6 PA6(1) 0 OC2 OC1 5 PA5 0 OC3 OC1 4 PA4(1) 0 OC4 OC1 3 PA3 Hi-Z IC4/OC5 OC1 2 PA2 Hi-Z IC1 -- 1 PA1 Hi-Z IC2 -- Bit 0 PA0 Hi-Z IC3 -- 1. This pin is not bonded in the 40-pin version. Figure 5-1. Port A Data Register (PORTA) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 61 Input/Output (I/O) Ports PORTA can be read any time. Inputs return the pin level, whereas outputs return the pin driver input level. If written, PORTA stores the data in an internal latch. It drives the pins only if they are configured as outputs. Writes to PORTA do not change the pin state when the pins are configured for timer output compares. Out of reset, port A bits 7 and 3-0 are general high-impedance inputs, while bits 6-4 are outputs, driving low. On bidirectional lines PA7 and PA3, the timer forces the I/O state to be an output if the associated output compare is enabled. In this case, the data direction bits DDRA7 and DDRA3 in PACTL will not be changed or have any effect on those bits. When the output compare functions associated with these pins are disabled, the DDR bits in PACTL govern the I/O state. 5.3 Port B Port B is an 8-bit, general-purpose I/O port with a data register (PORTB) and a data direction register (DDRB). * In the single-chip mode, port B pins are general-purpose I/O pins (PB7-PB0). * In the expanded-multiplexed mode, all of the port B pins act as the high-order address bits (A15-A8) of the address bus. 5.3.1 Port B Data Register Address: Read: Write: Reset: Alt. Func.: $0004 Bit 7 PB7 0 A15 6 PB6 0 A14 5 PB5 0 A13 4 PB4 0 A12 3 PB3 0 A11 2 PB2 0 A10 1 PB1 0 A9 Bit 0 PB0 0 A8 Figure 5-2. Port B Data Register (PORTB) PORTB can be read at any time. Inputs return the sensed levels at the pin, while outputs return the input level of the port B pin drivers. If PORTB is written, the data is stored in an internal latch and can be driven only if port B is configured for general-purpose outputs in single-chip or bootstrap mode. Port B pins are general--purpose inputs out of reset in single-chip and bootstrap modes. These pins are outputs (the high-order address bits) out of reset in expanded multiplexed and test modes. 5.3.2 Port B Data Direction Register Address: Read: Write: Reset: $0006 Bit 7 DDB7 0 6 DDB6 0 5 DDB5 0 4 DDB4 0 3 DDB3 0 2 DDB2 0 1 DDB1 0 Bit 0 DDB0 0 Figure 5-3. Data Direction Register for Port B (DDRB) DDB7-DDB0 -- Data Direction Bits for Port B 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured for input only MC68HC711D3 Data Sheet, Rev. 2.1 62 Freescale Semiconductor Port C 5.4 Port C Port C is an 8-bit, general-purpose I/O port with a data register (PORTC) and a data direction register (DDRC). In the single-chip mode, port C pins are general-purpose I/O pins (PC7-PC0). In the expanded-multiplexed mode, port C pins are configured as multiplexed address/data pins. During the address cycle, bits 7-0 of the address are output on PC7-PC0. During the data cycle, bits 7-0 (PC7-PC0) are bidirectional data pins controlled by the R/W signal. 5.4.1 Port C Control Register Address: Read: Write: Reset: $0002 Bit 7 0 0 6 0 0 5 CWOM 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 5-4. Port C Control Register (PIOC) CWOM -- Port C Wire-OR Mode Bit 1 = Port C outputs are open drain (to facilitate testing) 0 = Port C operates normally 5.4.2 Port C Data Register Address: Read: Write: Reset: $0003 Bit 7 PC7 0 6 PC6 0 5 PC5 0 4 PC4 0 3 PC3 0 2 PC2 0 1 PC1 0 Bit 0 PC0 0 Figure 5-5. Port C Data Register (PORTC) PORTC can be read at any time. Inputs return the sensed levels at the pin, while outputs return the input level of the port C pin drivers. If PORTC is written, the data is stored in an internal latch and can be driven only if port C is configured for general-purpose outputs in single-chip or bootstrap mode. Port C pins are general-purpose inputs out of reset in single-chip and bootstrap modes. These pins are multiplexed low-order address and data bus lines out of reset in expanded-multiplexed and test modes. 5.4.3 Port C Data Direction Register Address: Read: Write: Reset: $0007 Bit 7 DDC7 0 6 DDC6 0 5 DDC5 0 4 DDC4 0 3 DDC3 0 2 DDC2 0 1 DDC1 0 Bit 0 DDC0 0 Figure 5-6. Data Direction Register for Port C (DDRC) DDC7-DDC0 -- Data Direction Bits for Port C 1 = Corresponding port C pin is configured as output 0 = Corresponding port C pin is configured for input only MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 63 Input/Output (I/O) Ports 5.5 Port D Port D is an 8-bit, general-purpose I/O port with a data register (PORTD) and a data direction register (DDRD). The eight port D bits (D7-D0) can be used for general-purpose I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI) subsystems, or for bus data direction control 5.5.1 Port D Data Register Address: Read: Write: Reset: $0008 Bit 7 PD7 0 6 PD6 0 5 PD5 0 4 PD4 0 3 PD3 0 2 PD2 0 1 PD1 0 Bit 0 PD0 0 Figure 5-7. Port D Data Register (PORTD) PORTD can be read at any time and inputs return the sensed levels at the pin; whereas, outputs return the input level of the port D pin drivers. If PORTD is written, the data is stored in an internal latch, and can be driven only if port D is configured as general-purpose output. This port shares functions with the on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow on the bus in expanded and special test modes. 5.5.2 Port D Data Direction Register Address: Read: Write: Reset: $0009 Bit 7 DDD7 0 6 DDD6 0 5 DDD5 0 4 DDD4 0 3 DDD3 0 2 DDD2 0 1 DDD1 0 Bit 0 DDD0 0 Figure 5-8. Data Direction Register for Port D (DDRD) DDD7-DDD0 -- Data Direction for Port D When port D is a general-purpose I/O port, the DDRD register controls the direction of the I/O pins as follows: 0 = Configures the corresponding port D pin for input only 1 = Configures the corresponding port D pin for output In expanded and test modes, bits 6 and 7 are dedicated AS and R/W. When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master mode, DDD5 affects port D bit 5 as follows: 0 = Port D bit 5 is an error-detect input to the SPI. 1 = Port D bit 5 is configured as a general-purpose output line. If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3, and 4 are set. MC68HC711D3 Data Sheet, Rev. 2.1 64 Freescale Semiconductor Chapter 6 Serial Communications Interface (SCI) 6.1 Introduction The serial communications interface (SCI) is a universal asynchronous receiver transmitter (UART), one of two independent serial input/output (I/O) subsystems in the MC68HC711D3. It has a standard non-return to zero (NRZ) format (one start, eight or nine data, and one stop bit). Several baud rates are available. The SCI transmitter and receiver are independent, but use the same data format and bit rate. 6.2 Data Format The serial data format requires these conditions: * An idle line in the high state before transmission or reception of a message * A start bit, logic 0, transmitted or received, that indicates the start of each character * Data that is transmitted and received least significant bit (LSB) first * A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. * A break, defined as the transmission or reception of a logic 0 for some multiple number of frames Selection of the word length is controlled by the M bit in the SCI control register 1 (SCCR1). 6.3 Transmit Operation The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift register that puts data from the SCDR into serial form. The contents of the serial shift register can only be written through the SCDR. This double-buffered operation allows a character to be shifted out serially while another character is waiting in the SCDR to be transferred into the serial shift register. The output of the serial shift register is applied to PD1 as long as transmission is in progress or the transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set. The block diagram, Figure 6-1, shows the transmit serial shift register and the buffer logic at the top of the figure. 6.4 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers it to a parallel receive data register (SCDR) as a complete word. Refer to Figure 6-2. This double-buffered operation allows a character to be shifted in serially while another character is already in the SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 65 Serial Communications Interface (SCI) TRANSMITTER BAUD RATE CLOCK (WRITE ONLY) SCDR Tx BUFFER DDD1 10 (11) - BIT Tx SHIFT REGISTER H (8) 7 6 5 4 3 2 1 0 L PIN BUFFER AND CONTROL PD1 TxD SIZE 8/9 JAM ENABLE TRANSFER Tx BUFFER PREAMBLE--JAM 1s BREAK--JAM 0s SHIFT ENABLE FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC WAKE TC RDRF TDRE IDLE OR NF R8 SCCR1 SCI CONTROL 1 SCSR INTERRUPT STATUS TDRE TIE TC TCIE RWU TCIE SBK ILIE RIE TIE FE T8 M SCCR2 SCI CONTROL 2 SCI Rx REQUESTS SCI INTERRUPT REQUEST RE TE INTERNAL DATA BUS Figure 6-1. SCI Transmitter Block Diagram MC68HC711D3 Data Sheet, Rev. 2.1 66 Freescale Semiconductor Receive Operation 16X BAUD RATE CLOCK DDD0 STOP 10 (11) - BIT Rx SHIFT REGISTER (8) 7 6 5 4 3 2 1 0 ALL 1s START (READ ONLY) INTERNAL DATA BUS /16 PD0 RxD PIN BUFFER AND CONTROL DISABLE DRIVER RE DATA RECOVERY MSB M WAKEUP LOGIC RWU WAKE RDRF TDRE IDLE OR R8 TC NF T8 FE M SCCR1 SCI CONTROL 1 SCSR SCI STATUS 1 SCDR Rx BUFFER RDRF RIE IDLE ILIE OR RIE RWU TCIE SBK ILIE RIE TIE SCCR2 SCI CONTROL 2 SCI Tx REQUESTS SCI INTERRUPT REQUEST Figure 6-2. SCI Receiver Block Diagram MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 67 RE TE Serial Communications Interface (SCI) 6.5 Wakeup Feature The wakeup feature reduces SCI service overhead in multiple receiver systems. Software for each receiver evaluates the first character of each message. The receiver is placed in wakeup mode by writing a 1 to the RWU bit in the SCCR2 register. While RWU is 1, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). Although RWU can be cleared by a software write to SCCR2, to do so would be unusual. Normally, RWU is set by software and is cleared automatically with hardware. Whenever a new message begins, logic alerts the sleeping receivers to wake up and evaluate the initial character of the new message. Two methods of wakeup are available: * Idle line wakeup * Address mark wakeup During idle line wakeup, a sleeping receiver awakens as soon as the RxD line becomes idle. In the address mark wakeup, logic 1 in the most significant bit (MSB) of a character wakes up all sleeping receivers. 6.5.1 Idle-Line Wakeup To use the receiver wakeup method, establish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of receivers. This addressing scheme can take any form as long as all transmitting and receiving devices are programmed to understand the same scheme. Because the addressing information is usually the first frame(s) in a message, receivers that are not part of the current task do not become burdened with the entire set of addressing frames. All receivers are awake (RWU = 0) when each message begins. As soon as a receiver determines that the message is not intended for it, software sets the RWU bit (RWU = 1), which inhibits further flag setting until the RxD line goes idle at the end of the message. As soon as an idle line is detected by receiver logic, hardware automatically clears the RWU bit so that the first frame of the next message can be received. This type of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time between frames in a message. 6.5.2 Address-Mark Wakeup The serial characters in this type of wakeup consist of seven (eight if M = 1) information bits and an MSB, which indicates an address character (when set to 1 -- mark). The first character of each message is an addressing character (MSB = 1). All receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver. As soon as a receiver determines that a message is not intended for it, the receiver activates the RWU function by using a software write to set the RWU bit. Because setting RWU inhibits receiver-related flags, there is no further software overhead for the rest of this message. When the next message begins, its first character has its MSB set, which automatically clears the RWU bit and enables normal character reception. The first character whose MSB is set is also the first character to be received after wakeup because RWU gets cleared before the stop bit for that frame is serially received. This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. MC68HC711D3 Data Sheet, Rev. 2.1 68 Freescale Semiconductor SCI Error Detection 6.6 SCI Error Detection Three error conditions can occur during generation of SCI system interrupts: * Serial communications data register (SCDR) overrun * Received bit noise * Framing Three bits (OR, NF, and FE) in the serial communications status register (SCSR) indicate if one of these error conditions exists. The overrun error (OR) bit is set when the next byte is ready to be transferred from the receive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When an overrun error occurs, the data that caused the overrun is lost and the data that was already in SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the SCDR. The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of the SCDR. When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is set at the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor only recognizes the overrun error. The framing error flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of the SCDR. 6.7 SCI Registers This subsection describes the five addressable registers in the SCI. 6.7.1 SCI Data Register The SCI data register (SCDR) is a parallel register that performs two functions. It is the receive data register when it is read, and the transmit data register when it is written. Reads access the receive data buffer and writes access the transmit data buffer. Receive and transmit are double buffered. Address: Read: Write: Reset: $002F Bit 7 R7/T7 6 R6/T6 5 R5/T5 4 R4/T4 3 R3/T3 2 R2/T2 1 R1/T1 Bit 0 R0/T0 Unaffected by reset Figure 6-3. SCI Data Register (SCDR) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 69 Serial Communications Interface (SCI) 6.7.2 SCI Control Register 1 The SCI control register 1 (SCCR1) provides the control bits that determine word length and select the method used for the wakeup feature. Address: Read: Write: Reset: $002C Bit 7 R8 U U = Unaffected 6 T8 U 5 0 0 4 M 0 3 WAKE 0 2 0 0 1 0 0 Bit 0 0 0 Figure 6-4. SCI Control Register 1 (SCCR1) R8 -- Receive Data Bit 8 If M bit is set, R8 stores the ninth bit in the receive data character. T8 -- Transmit Data Bit 8 If M bit is set, T8 stores ninth bit in transmit data character. M -- Mode Bit The mode bit selects character format 0 = Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE -- Wakeup by Address Mark/Idle Bit 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mark (most significant data bit set) 6.7.3 SCI Control Register 2 The SCI control register 2 (SCCR2) provides the control bits that enable or disable individual SCI functions. Address: Read: Write: Reset: $002D Bit 7 TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 Figure 6-5. SCI Control Register 2 (SCCR2) TIE -- Transmit Interrupt Enable Bit 1 = TDRE interrupts disabled 1 = SCI interrupt requested when TDRE status flag is set TCIE -- Transmit Complete Interrupt Enable Bit 0 = TC interrupts disabled 1 = SCI interrupt requested when TC status flag is set RIE -- Receiver Interrupt Enable Bit 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set MC68HC711D3 Data Sheet, Rev. 2.1 70 Freescale Semiconductor SCI Registers ILIE -- Idle Line Interrupt Enable Bit 1 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE -- Transmitter Enable Bit When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble. 0 = Transmitter disabled 1 = Transmitter enabled RE -- Receiver Enable Bit 0 = Receiver disabled 1 = Receiver enabled RWU -- Receiver Wakeup Control Bit 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK -- Send Break Bit At least one character time of break is queued and sent each time SBK is written to 1. More than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud rate clock edge could occur between writing the 1 and writing the 0 to SBK. 0 = Break generator off 1 = Break codes generated as long as SBK = 1 6.7.4 SCI Status Register The SCI status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. Address: Read: Write: Reset: $002E Bit 7 TDRE 1 6 TC 1 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 Bit 0 0 0 Figure 6-6. SCI Status Register (SCSR) TDRE -- Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR. 0 = SCDR busy 1 = SCDR empty TC -- Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR. 0 = Transmitter busy 1 = Transmitter idle RDRF -- Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading SCSR with RDRF set and then reading SCDR. 0 = SCDR empty 1 = SCDR full MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 71 Serial Communications Interface (SCI) IDLE -- Idle Line Detected Flag This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR. 0 = RxD line active 1 = RxD line idle OR -- Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR. 0 = No overrun 1 = Overrun detected NF -- Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR. 0 = Unanimous decision 1 = Noise detected FE -- Framing Error Bit FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR. 0 = Stop bit detected 1 = Zero detected 6.7.5 Baud Rate Register The baud rate register (BAUD) is used to select different baud rates for the SCI system. The SCP1 and SCP0 bits function as a prescaler for the SCR2-SCR0 bits. Together, these five bits provide multiple baud rate combinations for a given crystal frequency. Normally, this register is written once during initialization. The prescaler is set to its fastest rate by default out of reset and can be changed at any time. Refer to Table 6-1 and Table 6-2 for normal baud rate selections. Address: Read: Write: Reset: $002B Bit 7 TCLR 0 U = Unaffected 6 0 0 5 SCP1 0 4 SCP0 0 3 RCKB 0 2 SCR2 U 1 SCR1 U Bit 0 SCR0 U Figure 6-7. Baud Rate Register (BAUD) TCLR -- Clear Baud Rate Counters (Test) RCKB -- SCI Baud Rate Clock Check (Test) MC68HC711D3 Data Sheet, Rev. 2.1 72 Freescale Semiconductor SCI Registers SCP1 and SCP0 -- SCI Baud Rate Prescaler Select Bits These two bits select a prescale factor for the SCI baud rate generator that determines the highest possible baud rate. Table 6-1. Baud Rate Prescale Selects SCP1 and SCP0 00 01 10 11 Divide Internal Clock By 1 3 4 13 Crystal Frequency in MHz 4.0 MHz (Baud) 62.50 K 20.83 K 15.625 K 4800 8.0 MHz (Baud) 125.0 K 41.67 K 31.25 K 9600 10.0 MHz (Baud) 156.25 K 52.08 K 38.4 K 12.02 K 12.0 MHz (Baud) 187.5 K 62.5 K 46.88 K 14.42 K SCR2-SCR0 -- SCI Baud Rate Select Bits These three bits select receiver and transmitter bit rate based on output from baud rate prescaler stage. Table 6-2. Baud Rate Selects SCR2-SCR0 000 001 010 011 100 101 110 111 Divide Prescaler By 1 2 4 8 16 32 64 128 Highest Baud Rate (Prescaler Output from Table 6-1) 4800 4800 2400 1200 600 300 150 -- -- 9600 9600 4800 2400 1200 600 300 150 -- 38.4 K 38.4 K 19.2 K 9600 4800 2400 1200 600 300 The prescale bits, SCP1 and SCP0, determine the highest baud rate and the SCR2-SCR0 bits select an additional binary submultiple (/1, /2, /4, through /128) of this highest baud rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The SCR2-SCR0 bits are not affected by reset and can be changed at any time, although they should not be changed when any SCI transfer is in progress. Figure 6-8 illustrates the SCI baud rate timing chain. The prescale select bits determine the highest baud rate. The rate select bits determine additional divide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 73 Serial Communications Interface (SCI) EXTAL OSCILLATOR AND CLOCK GENERATOR (/ 4) /3 INTERNAL BUS CLOCK (PH2) XTAL /4 / 13 SCP1 AND SCP0 E AS 0:0 0:1 1:0 1:1 SCR2-SCR0 0:0:0 /2 0:0:1 /2 0:1:0 /2 0:1:1 / 16 /2 1:0:0 SCI TRANSMIT BAUD RATE (1X) /2 1:0:1 /2 1:1:0 /2 1:1:1 SCI RECEIVE BAUD RATE (16X) Figure 6-8. SCI Baud Rate Diagram MC68HC711D3 Data Sheet, Rev. 2.1 74 Freescale Semiconductor Status Flags and Interrupts 6.8 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present. Status flags are automatically set by hardware logic conditions, but must be cleared by software, which provides an interlock mechanism that enables logic to know when software has noticed the status indication. The software clearing sequence for these flags is automatic -- functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an interrupt is requested. The TC flag indicates the transmitter has completed the queue. The TCIE bit is the local interrupt mask for TC. When TCIE is 0, TC must be polled; when TCIE is 1 and TC is 1, an interrupt is requested. Writing a 0 to TE requests that the transmitter stop when it can. The transmitter completes any transmission in progress before actually shutting down. Only an MCU reset can cause the transmitter to stop and shut down immediately. If TE is written to 0 when the transmitter is already idle, the pin reverts to its general-purpose I/O function (synchronized to the bit-rate clock). If anything is being transmitted when TE is written to 0, that character is completed before the pin reverts to general-purpose I/O, but any other characters waiting in the transmit queue are lost. The TC and TDRE flags are set at the completion of this last character, even though TE has been disabled. The SCI receiver has five status flags, three of which can generate interrupt requests. The status flags are set by the SCI logic in response to specific conditions in the receiver. These flags can be read (polled) at any time by software. Refer to Figure 6-9, which shows SCI interrupt arbitration. When an overrun takes place, the new character is lost, and the character that was in its way in the parallel RDR is undisturbed. RDRF is set when a character has been received and transferred into the parallel RDR. The OR flag is set instead of RDRF if overrun occurs. A new character is ready to be transferred into RDR before a previous character is read from RDR. The NF and FE flags provide additional information about the character in the RDR, but do not generate interrupt requests. The last receiver status flag and interrupt source come from the IDLE flag. The RxD line is idle if it has constantly been at logic 1 for a full character time. The IDLE flag is set only after the RxD line has been busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 75 Serial Communications Interface (SCI) BEGIN FLAG RDRF = 1? N Y OR = 1? N Y RIE = 1? N Y RE = 1? N Y TDRE = 1? N Y TIE = 1? N Y TE = 1? N Y TC = 1? N Y TCIE = 1? N Y IDLE = 1? N Y ILIE = 1? N Y RE = 1? N Y NO VALID SCI REQUEST VALID SCI REQUEST Figure 6-9. Interrupt Source Resolution within SCI MC68HC711D3 Data Sheet, Rev. 2.1 76 Freescale Semiconductor Chapter 7 Serial Peripheral Interface (SPI) 7.1 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the microcontroller unit (MCU) to communicate synchronously with peripheral devices, such as: * Transistor-transistor logic (TTL) shift registers * Liquid crystal diode (LCD) display drivers * Analog-to-digital converter (ADC) subsystems * Other microprocessors (MCUs) The SPI is also capable of inter-processor communication in a multiple master system. The SPI system can be configured as either a master or a slave device with data rates as high as one half of the E-clock rate when configured as master, and as fast as the E-clock rate when configured as slave. 7.2 Functional Description The central element in the SPI system is the block containing the shift register and the read data buffer. The system is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occurs. A single MCU register address is used for reading data from the read data buffer, and for writing data to the shifter. The SPI status block represents the SPI status functions (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR). Refer to Figure 7-1, which shows the SPI block diagram. 7.3 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the select line can optionally be used to indicate a multiple master bus contention. Refer to Figure 7-2. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 77 Serial Peripheral Interface (SPI) PH2 (INTERNAL) S M MISO PD2 /2 8-BIT SHIFT REGISTER READ DATA BUFFER CLOCK SELECT SPI CLOCK (MASTER) CLOCK LOGIC M S PIN CONTROL LOGIC DIVIDER /4 /16 /32 MSB LSB S M MOSI PD3 SCK PD4 SPR1 SPR0 SS PD5 DWOM MSTR MSTR SPI CONTROL SPE WCOL MODF SPIF DWOM MSTR CPHA CPOL SPR1 SPI STATUS REGISTER 8 SPI CONTROL REGISTER SPI INTERRUPT REQUEST INTERNAL DATA BUS Figure 7-1. SPI Block Diagram MC68HC711D3 Data Sheet, Rev. 2.1 78 Freescale Semiconductor SPR0 SPIE SPE SPE Clock Phase and Polarity Controls SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE) SLAVE CPHA=1 TRANSFER IN PROGRESS 3 1. SS ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED MASTER TRANSFER IN PROGRESS 2 SLAVE CPHA=0 TRANSFER IN PROGRESS 1 5 4 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 1 2 3 4 5 6 7 8 Figure 7-2. SPI Transfer Format 7.4 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. When CPHA equals 0, the slave select (SS) line must be negated and reasserted between each successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is active low, a write collision error results. When CPHA equals 1, the SS line can remain low between successive transfers. 7.5 SPI Signals This subsection contains description of the four SPI signals: * Master in/slave out (MISO) * Master out/slave in (MOSI) * Serial clock (SCK) * Slave select (SS) 7.5.1 Master In/Slave Out (MISO) MISO is one of two unidirectional serial data signals. It is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 79 Serial Peripheral Interface (SPI) 7.5.2 Master Out/Slave In (MOSI) The MOSI line is the second of the two unidirectional serial data signals. It is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. 7.5.3 Serial Clock (SCK) SCK, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the MOSI and MISO lines. Master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Four possible timing relationships can be chosen by using control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The SPI clock rate select bits, SPR1 and SPR0, in the SPCR of the master device, select the clock rate. In a slave device, SPR1 and SPR0 have no effect on the operation of the SPI. 7.5.4 Slave Select (SS) The SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. If it goes low, a mode fault error flag (MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault circuit, write a 1 in bit 5 of the port D data direction register. This sets the SS pin to act as a general-purpose output. The other three lines are dedicated to the SPI whenever the serial peripheral interface is on. The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should be identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line can be tied to VSS as long as only CPHA = 1 clock mode is used. 7.6 SPI System Errors Two system errors can be detected by the SPI system. The first type of error arises in a multiple-master system when more than one SPI device simultaneously tries to be a master. This error is called a mode fault. The second type of error, write collision, indicates that an attempt was made to write data to the SPDR while a transfer was in progress. When the SPI system is configured as a master and the SS input line goes to active low, a mode fault error has occurred -- usually because two devices have attempted to act as master at the same time. In cases where more than one device is concurrently configured as a master, there is a chance of contention between two pin drivers. For push-pull CMOS drivers, this contention can cause permanent damage. The mode fault attempts to protect the device by disabling the drivers. The MSTR control bit in the SPCR and all four DDRD control bits associated with the SPI are cleared. An interrupt is generated subject to masking by the SPIE control bit and the I bit in the CCR. Other precautions may need to be taken to prevent driver damage. If two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. The amount of damage possible depends on the length of time both devices attempt to act as master. MC68HC711D3 Data Sheet, Rev. 2.1 80 Freescale Semiconductor SPI Registers A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is not double buffered in the transmit direction, writes to SPDR cause data to be written directly into the SPI shift register. Because this write corrupts any transfer in progress, a write collision error is generated. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. A write collision is normally a slave error because a slave has no control over when a master initiates a transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate a write-collision error, although the SPI logic can detect write collisions in both master and slave devices. The SPI configuration determines the characteristics of a transfer in progress. For a master, a transfer begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA equal to zero, a transfer starts when SS goes low and ends when SS returns high. In this case, SPIF is set at the middle of the eighth SCK cycle when data is transferred from the shifter to the parallel data register, but the transfer is still in progress until SS goes high. For a slave with CPHA equal to one, transfer begins when the SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals one when SPIF is set. For a slave, after a byte transfer, SCK must be in inactive state for at least 2 E-clock cycles before the next byte transfer begins. 7.7 SPI Registers The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions. This sub-section provides a description of how these registers are organized. 7.7.1 SPI Control Register Address: Read: Write: Reset: $0028 Bit 7 SPIE 0 U = Unaffected 6 SPE 0 5 DWOM 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 U Bit 0 SPR0 U Figure 7-3. SPI Control Register (SPCR) SPIE -- Serial Peripheral Interrupt Enable Bit 0 = SPI interrupt disabled 1 = SPI interrupt enabled SPE -- Serial Peripheral System Enable Bit 0 = SPI off 1 = SPI on DWOM -- Port D Wired-OR Mode Bit DWOM affects all six port D pins. 0 = Normal CMOS outputs 1 = Open-drain outputs MSTR -- Master Mode Select Bit 0 = Slave mode 1 = Master mode MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 81 Serial Peripheral Interface (SPI) CPOL -- Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 7-2 and 7.4 Clock Phase and Polarity Controls. CPHA -- Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure 7-2 and 7.4 Clock Phase and Polarity Controls. SPR1 and SPR0 -- SPI Clock Rate Select Bits These two serial peripheral rate bits select one of four baud rates to be used as SCK if the device is a master; however, they have no effect in the slave mode. Table 7-1. SPI Clock Rates SPR1 and SPR0 00 01 10 11 E Clock Divide By 2 4 16 32 Frequency at E = 2 MHz (Baud) 1.0 MHz 500 kHz 125 kHz 62.5 kHz 7.7.2 SPI Status Register Address: Read: Write: Reset: $0029 Bit 7 SPIF 0 6 WCOL 0 5 0 0 4 MODF 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 7-4. SPI Status Register (SPSR) SPIF -- SPI Transfer Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited. WCOL -- Write Collision Bit Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access of SPDR. Refer to 7.5.4 Slave Select (SS) and 7.6 SPI System Errors. 0 = No write collision 1 = Write collision Bit 5 -- Not implemented Always reads 0. MODF -- Mode Fault Bit To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to 7.5.4 Slave Select (SS) and 7.6 SPI System Errors. 0 = No mode fault 1 = Mode fault MC68HC711D3 Data Sheet, Rev. 2.1 82 Freescale Semiconductor SPI Registers Bits 3-0 -- Not implemented Always reads 0 7.7.3 SPI Data I/O Register The SPI data I/O register (SPDR) is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave devices. A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. Address: Read: Write: Reset: $002A Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset Figure 7-5. SPI Data I/O Register (SPDR) NOTE SPI is double buffered in and single buffered out. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 83 Serial Peripheral Interface (SPI) MC68HC711D3 Data Sheet, Rev. 2.1 84 Freescale Semiconductor Chapter 8 Programmable Timer 8.1 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale rate. The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this main clocking chain drive circuitry that generates the slower clocks used by the pulse accumulator, the real-time interrupt (RTI), and the computer operating properly (COP) watchdog subsystems. Refer to Figure 8-1. All main timer system activities are referenced to this free-running counter. The counter begins incrementing from $0000 as the microcontroller unit (MCU) comes out of reset, and continues to the maximum count, $FFFF. At the maximum count, the counter rolls over to $0000, sets an overflow flag, and continues to increment. As long as the MCU is running in a normal operating mode, there is no way to reset, change, or interrupt the counting. The capture/compare subsystem features three input capture channels, four output compare channels, and one channel that can be selected to perform either input capture or output compare. Each of the three input capture functions has its own 16-bit input capture register (time capture latch) and each of the output compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI have their own interrupt controls and separate interrupt vectors. The pulse accumulator contains an 8-bit counter and edge select logic. The pulse accumulator can operate in either event counting or gated time accumulation modes. During event counting mode, the pulse accumulator's 8-bit counter increments when a specified edge is detected on an input signal. During gated time accumulation mode, an internal clock source increments the 8-bit counter while an input signal has a predetermined logic level. RTI is a programmable periodic interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates. The COP watchdog clock input (E/215) is tapped off of the free-running counter chain. The COP automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system. Refer to Table 8-1 for crystal related frequencies and periods. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 85 Programmable Timer OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) AS E CLOCK INTERNAL BUS CLOCK (PH2) PRESCALER (/ 2, 4, 16, 32) SPR1 AND SPR0 SPI PRESCALER (/ 1, 3, 4, 13) SCP1 AND SCP0 E/2 6 PRESCALER (/ 1, 2, 4,....128) SCR2-SCR0 /16 SCI RECEIVER CLOCK SCI TRANSMIT CLOCK PULSE ACCUMULATOR E / 213 PRESCALER (/ 1, 2, 4, 8) RTR1 AND RTR0 /4 E/215 REAL-TIME INTERRUPT PRESCALER (/ 1, 4, 8, 16) PR1 AND PR0 PRESCALER (/1, 4, 16, 64) CR1 AND CR0 TOF FF1 S R Q Q S R TCNT FF2 Q Q FORCE COP RESET IC/OC CLEAR COP TIMER SYSTEM RESET Figure 8-1. Timer Clock Divider Chains MC68HC711D3 Data Sheet, Rev. 2.1 86 Freescale Semiconductor Timer Structure Table 8-1. Timer Summary Control Bits PR1 and PR0 00 1 count -- overflow -- 01 1 count -- overflow -- 10 1 count -- overflow -- 11 1 count -- overflow -- 1.0 s 65.536 ms 4.0 s 262.14 ms 8.0 s 524.29 ms 16.0 s 1.049 s 4.0 MHz 1.0 MHz 1000 ns XTAL Frequencies 8.0 MHz 12.0 MHz 2.0 MHz 3.0 MHz 500 ns 333 ns Main Timer Count Rates 500 ns 32.768 ms 2.0 s 131.07 ms 4.0 s 262.14 ms 8.0 s 524.29 ms 333 ns 21.845 ms 1.333 s 87.381 ms 2.667 s 174.76 ms 5.333 s 349.52 ms Other Rates (E) (1/E) (E/1) (E/216) (E/4) (E/218) (E/8) (E/219) (E/16) (E/220) 8.2 Timer Structure Figure 8-2 shows the capture/compare system block diagram. The port A pin control block includes logic for timer functions and for general-purpose input/output (I/O). For pins PA2, PA1, and PA0, this block contains both the edge-detection logic and the control logic that enables the selection of which edge triggers an input capture. The digital level on PA2-PA0 can be read at any time (read PORTA register), even if the pin is being used for the input capture function. Pins PA6-PA4 are used for either general-purpose output or as output compare pins. Pin PA3 can be used for general-purpose I/O, input capture 4, output compare 5, or output compare 1. When one of these pins is being used for an output compare function, it cannot be written directly as if it were a general-purpose output. Each of the output compare functions (OC5-OC2) is related to one of the port A output pins. Output compare 1 (OC1) has extra control logic, allowing it optional control of any combination of the PA7-PA3 pins. The PA7 pin can be used as a general-purpose I/O pin, as an input to the pulse accumulator, or as an OC1 output pin. 8.3 Input Capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched values and use them to compute the periodicity and duration of events. For example, by storing the times of successive edges of an incoming signal, software can determine the period and pulse width of a signal. To measure period, two successive edges of the same polarity are captured. To measure pulse width, two alternate polarity edges are captured. In most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to the PH2 clock. These asynchronous capture requests are synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from when the timer counter is being incremented. This synchronization process introduces a delay from when the edge occurs to when the counter value is detected. Because these delays offset each other when the time between two edges is being measured, the delay can be ignored. When an input capture is being used with an output compare, there is a similar delay between the actual compare point and when the output pin changes state. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 87 Programmable Timer MCU E CLOCK PRESCALER -- DIVIDE BY 1, 4, 8, 16 PR1 PR0 TCNT (HI) TCNT (LO) TOI TOF 16-BIT FREE RUNNING COUNTER 9 16-BIT TIMER BUS TAPS FOR RTL, COP WATCHDOG, AND PULSE ACCUMULATOR FORCE OUTPUT COMPARE FOC1 OC2I OC1I INTERRUPT REQUESTS (FURTHER QUALIFIED BY I BIT IN CCR) TO PULSE ACCUMULATOR 8 BIT 7 7 BIT 6 PA6/OC2/ OC1 PORT A PINS PA7/OC1/ PAI 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) OC1F 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) OC2F FOC2 OC3I 6 BIT 5 OC4I 5 BIT 4 I4/O5I 4 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) OC3F FOC3 PA5/OC3/ OC1 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) OC4F FOC4 OC5 I4/O5F IC4 CFORC I4/O5 IC1I 3 BIT 2 IC2I IC2F IC3I IC3F TFLG 1 STATUS FLAGS TMSK 1 INTERRUPT ENABLES 1 BIT 0 PORT A PIN CONTROL 2 BIT 1 FOC5 PA4/OC4/ OC1 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) CLK BIT 3 PA3/IC4/ OC5/OC1 16-BIT LATCH 16-BIT LATCH TIC1 (HI) CLK IC1F PA2/IC1 TIC1 (LO) CLK 16-BIT LATCH TIC2 (HI) PA1/IC2 TIC2 (LO) CLK 16-BIT LATCH TIC3 (HI) PA0/IC3 TIC3 (LO) Figure 8-2. Capture/Compare Block Diagram The control and status bits that implement the input capture functions are contained in the PACTL, TCTL2, TMSK1, and TFLG1 registers. To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. MC68HC711D3 Data Sheet, Rev. 2.1 88 Freescale Semiconductor Input Capture 8.3.1 Timer Control 2 Register Use the control bits of timer control 2 register (TCTL2) to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. Each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture function. The input capture functions operate independently of each other and can capture the same TCNT value if the input edges are detected within the same timer count cycle. Address: Read: Write: Reset: $0021 Bit 7 EDG4B 0 6 EDG4A 0 5 EDG1B 0 4 EDG1A 0 3 EDG2B 0 2 EDG2A 0 1 EDG3B 0 Bit 0 EDG3A 0 Figure 8-3. Timer Control 2 Register (TCTL2) EDGxB and EDGxA -- Input Capture Edge Control There are four pairs of these bits. Each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in PACTL is set. Refer to Table 8-2 for timer control configuration. Table 8-2. Timer Control Configuration EDGxB 0 0 1 1 EDGxA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge 8.3.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase two clock so that the count value is stable whenever a capture occurs. The timer input capture (TICx) registers are not affected by reset. Input capture values can be read from a pair of 8-bit read-only registers. A read of the high-order byte of an input capture register pair inhibits a new capture transfer for one bus cycle. If a double-byte read instruction, such as LDD, is used to read the captured value, coherency is assured. When a new input capture occurs immediately after a high-order byte read, transfer is delayed for an additional cycle but the value is not lost. Address: $0010 -- TIC1 (High) Bit 15 14 13 Read: Bit 15 Bit 14 Bit 13 Write: Reset: = Unimplemented 12 Bit 12 11 Bit 11 10 Bit 10 9 Bit 9 Bit 8 Bit 8 Unaffected by reset Figure 8-4. Timer Input Capture Registers (TICx) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 89 Programmable Timer Address: $0011 -- TIC1 (Low) Bit 7 6 5 Read: Bit 7 Bit 6 Bit 5 Write: Reset: Address: $0012 -- TIC2 (High) Bit 15 14 13 Read: Bit 15 Bit 14 Bit 13 Write: Reset: Address: $0013 -- TIC2 (Low) Bit 7 6 5 Read: Bit 7 Bit 6 Bit 5 Write: Reset: Address: $0014 -- TIC3 (High) Bit 15 14 13 Read: Bit 15 Bit 14 Bit 13 Write: Reset: Address: $0015 -- TIC3 (Low) Bit 7 6 5 Read: Bit 7 Bit 6 Bit 5 Write: Reset: = Unimplemented 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset 12 Bit 12 11 Bit 11 10 Bit 10 9 Bit 9 Bit 8 Bit 8 Unaffected by reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset 12 Bit 12 11 Bit 11 10 Bit 10 9 Bit 9 Bit 8 Bit 8 Unaffected by reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset Figure 8-4. Timer Input Capture Registers (TICx) (Continued) 8.3.3 Timer Input Capture 4/Output Compare 5 Register Use timer input capture 4/output compare 5 (TI4/O5) as either an input capture register or an output compare register, depending on the function chosen for the I4/O5 pin. To enable it as an input capture pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level 1. To use it as an output compare register, set the I4/O5 bit to a logic level 0. Refer to 8.7 Pulse Accumulator. Address: $001E -- TI4/O5 (High) Bit 15 14 13 Read: Bit 15 Bit 14 Bit 13 Write: Reset: 1 1 1 Address: $001F -- TI4/O5 (Low) Bit 7 6 5 Read: Bit 7 Bit 6 Bit 5 Write: Reset: 1 1 1 = Unimplemented 12 Bit 12 1 4 Bit 4 1 11 Bit 11 1 3 Bit 3 1 10 Bit 10 1 2 Bit 2 1 9 Bit 9 1 1 Bit 1 1 Bit 8 Bit 8 1 Bit 0 Bit 0 1 Figure 8-5. Timer Input Capture 4/Output Compare 5 Register (TI4/O5) MC68HC711D3 Data Sheet, Rev. 2.1 90 Freescale Semiconductor Output Compare (OC) 8.4 Output Compare (OC) Use the output compare (OC) function to program an action to occur at a specific time -- when the 16-bit counter reaches a specified value. For each of the five output compare functions, there is a separate 16-bit compare register and a dedicated 16-bit comparator. The value in the compare register is compared to the value of the free-running counter on every bus cycle. When the compare register matches the counter value, an output compare status flag is set. The flag can be used to initiate the automatic actions for that output compare function. To produce a pulse of a specific duration, write to the output compare register a value representing the time the leading edge of the pulse is to occur. The output compare circuit is configured to set the appropriate output either high or low, depending on the polarity of the pulse being produced. After a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. A value representing the width of the pulse is added to the original value, and then is written to the output compare register. Because the pin state changes occur at specific values of the free-running counter, the pulse width can be controlled accurately at the resolution of the free-running counter, independent of software latencies. To generate an output signal of a specific frequency and duty cycle, repeat this pulse-generating procedure. There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and TOC4, and the TI4/O5 register, which functions under software control as either IC4 or OC5. Each of the OC registers is set to $FFFF on reset. A value written to an OC register is compared to the free-running counter value during each E-clock cycle. If a match is found, the particular output compare flag is set in timer interrupt flag register 1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask register 1 (TMSK1), an interrupt is generated. In addition to an interrupt, a specified action can be initiated at one or more timer output pins. For OC5-OC2, the pin action is controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken on each successful compare, regardless of whether the OCxF flag in the TFLG1 register was previously cleared. OC1 is different from the other output compares in that a successful OC1 compare can affect any or all five of the OC pins. The OC1 output action taken when a match is found is controlled by two 8-bit registers with three bits unimplemented: the output compare 1 mask register, OC1M, and the output compare 1 data register, OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies what data is placed on these port pins. 8.4.1 Timer Output Compare Registers All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset. If an output compare register is not used for an output compare function, it can be used as a storage location. A write to the high-order byte of an output compare register pair inhibits the output compare function for one bus cycle. This inhibition prevents inappropriate subsequent comparisons. Coherency requires a complete 16-bit read or write. However, if coherency is not needed, byte accesses can be used. For output compare functions, write a comparison value to output compare registers TOC1-TOC4 and TI4/O5. When TCNT value matches the comparison value, specified pin actions occur. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 91 Programmable Timer Address: $0016 -- TOC1 (High) Bit 15 14 Read: Bit 15 Bit 14 Write: Reset: 1 1 Address: $0017 -- TOC1 (Low) Bit 7 6 Read: Bit 7 Bit 6 Write: Reset: 1 1 Address: $0018 -- TOC2 (High) Bit 15 14 Bit 15 1 Bit 14 1 13 Bit 13 1 12 Bit 12 1 11 Bit 11 1 10 Bit 10 1 9 Bit 9 1 Bit 8 Bit 8 1 5 Bit 5 1 4 Bit 4 1 3 Bit 3 1 2 Bit 2 1 1 Bit 1 1 Bit 0 Bit 0 1 13 Bit 13 1 12 Bit 12 1 11 Bit 11 1 10 Bit 10 1 9 Bit 9 1 Bit 8 Bit 8 1 Read: Write: Reset: Address: $0019 -- TOC2 (Low) Bit 7 6 Read: Bit 7 Bit 6 Write: Reset: 1 1 Address: $001A -- TOC3 (High) Bit 15 14 Read: Bit 15 Bit 14 Write: Reset: 1 1 Address: $001B -- TOC3 (Low) Bit 7 6 Read: Bit 7 Bit 6 Write: Reset: 1 1 Address: $001C -- TOC4 (High) Bit 15 14 Read: Bit 15 Bit 14 Write: Reset: 1 1 Address: $001D -- TOC4 (Low) Bit 7 6 Read: Bit 7 Bit 6 Write: Reset: 1 1 5 Bit 5 1 4 Bit 4 1 3 Bit 3 1 2 Bit 2 1 1 Bit 1 1 Bit 0 Bit 0 1 13 Bit 13 1 5 Bit 5 1 12 Bit 12 1 4 Bit 4 1 11 Bit 11 1 3 Bit 3 1 10 Bit 10 1 2 Bit 2 1 9 Bit 9 1 1 Bit 1 1 Bit 8 Bit 8 1 Bit 0 Bit 0 1 13 Bit 13 1 12 Bit 12 1 11 Bit 11 1 10 Bit 10 1 9 Bit 9 1 Bit 8 Bit 8 1 5 Bit 5 1 4 Bit 4 1 3 Bit 3 1 2 Bit 2 1 1 Bit 1 1 Bit 0 Bit 0 1 Figure 8-6. Timer Output Capture Registers (TOCx) MC68HC711D3 Data Sheet, Rev. 2.1 92 Freescale Semiconductor Output Compare (OC) 8.4.2 Timer Compare Force Register The timer compare force register (CFORC) allows forced early compares. FOC1-FOC5 correspond to the five output compares. These bits are set for each output compare that is to be forced. The action taken as a result of a forced compare is the same as if there were a match between the OCx register and the free-running counter, except that the corresponding interrupt status flag bits are not set. The forced channels trigger their programmed pin actions to occur at the next timer count transition after the write to CFORC. The CFORC bits should not be used on an output compare function that is programmed to toggle its output on a successful compare because a normal compare that occurs immediately before or after the force can result in an undesirable operation. Address: Read: Write: Reset: $000B Bit 7 FOC1 0 6 FOC2 0 5 FOC3 0 4 FOC4 0 3 FOC5 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-7. Timer Compare Force Register (CFORC) FOC1-FOC5 -- Write 1s to Force Compare Bits 0 = Not affected 1 = Output x action occurs Bits 2-0 -- Not implemented, always read 0. 8.4.3 Output Compare 1 Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA7-PA3. Address: Read: Write: Reset: $000C Bit 7 OC1M7 0 6 OC1M6 0 5 OC1M5 0 4 OC1M4 0 3 OC1M3 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-8. Output Compare 1 Mask Register (OC1M) OC1M7-OC1M3 -- Output Compare Masks 0 = OC1 disabled 1 = OC1 enabled to control the corresponding pin of port A Bits 2-0 -- Not implemented; always read 0. Set bit(s) to enable OC1 to control corresponding pin(s) of port A. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 93 Programmable Timer 8.4.4 Output Compare 1 Data Register Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in OC1M. Address: Read: Write: Reset: $000D Bit 7 OC1D7 0 6 OC1D6 0 5 OC1D5 0 4 OC1D4 0 3 OC1D3 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-9. Output Compare 1 Data Register (OC1D) If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits 2-0 -- Not implemented; always read 0. 8.4.5 Timer Counter Register The 16-bit read-only timer count register (TCNT) contains the prescaled value of the 16-bit timer. A full counter read addresses the most significant byte (MSB) first. A read of this address causes the least significant byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the MSB read cycle. Address: $000E -- TCNT High Bit 15 14 Read: Bit 15 Bit 14 Write: Reset: 0 0 13 Bit 13 0 12 Bit 12 0 11 Bit 11 0 10 Bit 10 0 9 Bit 9 0 Bit 8 Bit 08 0 Address: $000F -- TCNT Low Bit 7 6 5 Read: Bit 7 Bit 6 Bit 5 Write: Reset: 0 0 0 = Unimplemented 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0 Figure 8-10. Timer Counter Registers (TCNT) In normal modes, TCNT is read-only. MC68HC711D3 Data Sheet, Rev. 2.1 94 Freescale Semiconductor Output Compare (OC) 8.4.6 Timer Control 1 Register The bits of the timer control 1 register (TCTL1) specify the action taken as a result of a successful OCx compare. Address: Read: Write: Reset: $0020 Bit 7 OM2 0 6 OL2 0 5 OM3 0 4 OL3 0 3 OM4 0 2 OL4 0 1 OM5 0 Bit 0 OL5 0 Figure 8-11. Timer Control 1 Register (TCTL1) OM2-OM5 -- Output Mode Bits OL2-OL5 -- Output Level Bits These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to Table 8-3 for the coding. Table 8-3. Timer Output Compare Actions OMx 0 0 1 1 OLx 0 1 0 1 Action Taken on Successful Compare Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to 0 Set OCx output line to 1 8.4.7 Timer Interrupt Mask 1 Register The timer interrupt mask 1 register (TMSK1) is an 8-bit register used to enable or inhibit the timer input capture and output compare interrupts. Address: Read: Write: Reset: $0022 Bit 7 OC1I 0 6 OC2I 0 5 OC3I 0 4 OC4I 0 3 I4/O5I 0 2 IC1I 0 1 IC2I 0 Bit 0 IC3I 0 Figure 8-12. Timer Interrupt Mask 1 Register (TMSK1) OC1I-OC4I -- Output Compare x Interrupt Enable Bits If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I -- Input Capture 4 or Output Compare 5 Interrupt Enable Bit When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit. IC1I-IC3I -- Input Capture x Interrupt Enable Bits If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. NOTE Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the corresponding interrupt sources. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 95 Programmable Timer 8.4.8 Timer Interrupt Flag 1 Register The timer interrupt flag 1 register (TFLG1) bits indicate when timer system events have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position. Address: Read: Write: Reset: $0023 Bit 7 OC1F 0 6 OC2F 0 5 OC3F 0 4 OC4F 0 3 I4/O5F 0 2 IC1F 0 1 IC2F 0 Bit 0 IC3F 0 Figure 8-13. Timer Interrupt Flag 1 Register (TFLG1) Clear flags by writing a 1 to the corresponding bit position(s). OC1F-OC5F -- Output Compare x Flag Set each time the counter matches output compare x value I4/O5F -- Input Capture 4/Output Compare 5 Flag Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL IC1F-IC3F -- Input Capture x Flag Set each time a selected active edge is detected on the ICx input line 8.4.9 Timer Interrupt Mask 2 Register The timer interrupt mask 1 register (TMSK2) is an 8-bit register used to enable or inhibit timer overflow and real-time interrupts. The timer prescaler control bits are included in this register. Address: Read: Write: Reset: $0024 Bit 7 TOI 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 0 0 2 0 0 1 PR1 0 Bit 0 PR0 0 Figure 8-14. Timer Interrupt Mask 2 Register (TMSK2) TOI -- Timer Overflow Interrupt Enable Bit 0 = TOF interrupts disabled 1 = Interrupt requested when TOF is set to 1 RTII -- Real-Time Interrupt Enable Bit Refer to 8.5 Real-Time Interrupt. PAOVI -- Pulse Accumulator Overflow Interrupt Enable Bit Refer to 8.7 Pulse Accumulator. PAII -- Pulse Accumulator Input Edge Interrupt Enable Bit Refer to 8.7 Pulse Accumulator. NOTE Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. MC68HC711D3 Data Sheet, Rev. 2.1 96 Freescale Semiconductor Output Compare (OC) PR1 and PR0 -- Timer Prescaler Select Bits These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be written once only, and the write must be within 64 cycles after reset. Refer to Table 8-4 for specific timing values. Table 8-4. Timer Prescale PR1 and PR0 00 01 10 11 Prescaler 1 4 8 16 8.4.10 Timer Interrupt Flag 2 Register The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position. Address: Read: Write: Reset: $0025 Bit 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2) Clear flags by writing a 1 to the corresponding bit position(s). TOF -- Timer Overflow Interrupt Flag Set when TCNT changes from $FFFF to $0000 RTIF -- Real-Time (Periodic) Interrupt Flag Refer to 8.5 Real-Time Interrupt. PAOVF -- Pulse Accumulator Overflow Interrupt Flag Refer to 8.7 Pulse Accumulator. PAIF -- Pulse Accumulator Input Edge Interrupt Flag Refer to 8.7 Pulse Accumulator. Bits 3-0 -- Not implemented Always read 0. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 97 Programmable Timer 8.5 Real-Time Interrupt The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR1 and RTR0. Refer to Table 8-5 for the periodic real-time interrupt rates. Table 8-5. Periodic Real-Time Interrupt Rates RTR1 and RTR0 00 01 10 11 E = 1 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms E = 2 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 3 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = X MHz (E/213) (E/214) (E/215) (E/216) The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except by reset. This clock causes the time between successive RTI timeouts to be a constant that is independent of the software latencies associated with flag clearing and service. For this reason, an RTI period starts from the previous timeout, not from when RTIF is cleared. Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated. After reset, one entire real-time interrupt period elapses before the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL registers. 8.5.1 Timer Interrupt Mask 2 Register The timer interrupt mask 2 register (TMSK2) contains the real-time interrupt enable bits. Address: Read: Write: Reset: $0024 Bit 7 TOI 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 0 0 2 0 0 1 PR1 0 Bit 0 PR0 0 Figure 8-16. Timer Interrupt Mask 2 Register (TMSK2) TOI -- Timer Overflow Interrupt Enable Bit Refer to 8.4 Output Compare (OC). RTII -- Real-Time Interrupt Enable Bit 0 = RTIF interrupts disabled 1 = Interrupt requested PAOVI -- Pulse Accumulator Overflow Interrupt Enable Bit Refer to 8.7 Pulse Accumulator. PAII -- Pulse Accumulator Input Edge Bit Refer to 8.7 Pulse Accumulator. Bits 3-2 -- Unimplemented Always read 0. MC68HC711D3 Data Sheet, Rev. 2.1 98 Freescale Semiconductor Real-Time Interrupt PR1 and PR0 -- Timer Prescaler Select Bits Refer to Table 8-4. NOTE Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. 8.5.2 Timer Interrupt Flag 2 Register Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position. Address: Read: Write: Reset: $0025 Bit 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2) Clear flags by writing a 1 to the corresponding bit position(s). TOF -- Timer Overflow Interrupt Flag Set when TCNT changes from $FFFF to $0000 RTIF -- Real-Time Interrupt Flag The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte to TFLG2 with bit 6 set. PAOVF -- Pulse Accumulator Overflow Interrupt Flag Refer to 8.7 Pulse Accumulator. PAIF -- Pulse Accumulator Input Edge Interrupt Flag Refer to 8.7 Pulse Accumulator. Bits 3-0 -- Not implemented Always read 0. 8.5.3 Pulse Accumulator Control Register Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the rate for the real-time interrupt system. Bit DDRA3 determines whether port A bit three is an input or an output when used for general-purpose I/O. The remaining bits control the pulse accumulator. Address: Read: Write: Reset: $0026 Bit 7 DDRA7 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 DDRA3 0 2 I4/O5 0 1 RTR1 0 Bit 0 RTR0 0 Figure 8-18. Pulse Accumulator Control Register (PACTL) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 99 Programmable Timer DDRA7 -- Data Direction Control for Port A Bit 7 Refer to 8.7 Pulse Accumulator. PAEN -- Pulse Accumulator System Enable Bit Refer to 8.7 Pulse Accumulator. PAMOD -- Pulse Accumulator Mode Bit Refer to 8.7 Pulse Accumulator. PEDGE -- Pulse Accumulator Edge Control Bit Refer to 8.7 Pulse Accumulator. DDRA3 -- Data Direction Register for Port A Bit 3 Refer to Chapter 5 Input/Output (I/O) Ports. I4/O5 -- Input Capture 4/Output Compare 5 Bit Refer to 8.3 Input Capture. RTR1 and RTR0 -- RTI Interrupt Rate Select Bits These two bits determine the rate at which the RTI system requests interrupts. The RTI system is driven by an E divided by 213 rate clock that is compensated so it is independent of the timer prescaler. These two control bits select an additional division factor. See Table 8-6. Table 8-6. Real-Time Interrupt Rates RTR1 and RTR0 00 01 10 11 E = 1 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms E = 2 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 3 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = X MHz (E/213) (E/214) (E/215) (E/216) 8.6 Computer Operating Properly Watchdog Function The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially related to the main timer system. The CR1 and CR0 bits in the OPTION register and the NOCOP bit in the CONFIG register determine the status of the COP function. Refer to Chapter 4 Resets, Interrupts, and Low-Power Modes for a more detailed discussion of the COP function. 8.7 Pulse Accumulator The MC68HC711D3 has an 8-bit counter that can be configured to operate either as a simple event counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Figure 8-19. In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. The maximum clocking rate for the external event counting mode is the E clock divided by two. In gated time accumulation mode, a free-running E-clock / 64 signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to Table 8-7. The pulse accumulator counter can be read or written at any time. Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as described here. MC68HC711D3 Data Sheet, Rev. 2.1 100 Freescale Semiconductor Pulse Accumulator 1 INTERRUPT REQUESTS 2 PAOVF PAI EDGE PAOVI TMSK2 INT ENABLES TFLG2 INTERRUPT STATUS PAIF PAII E / 64 CLOCK (FROM MAIN TIMER) DISABLE FLAG SETTING PA7/ PAI/OC1 INPUT BUFFER AND EDGE DETECTION OUTPUT BUFFER 2:1 MUX OVERFLOW PACNT 8-BIT COUNTER ENABLE PAEN FROM MAIN TIMER OC1 PAMOD DDRA7 PACTL CONTROL PEDGE PAEN INTERNAL DATA BUS Figure 8-19. Pulse Accumulator Table 8-7. Pulse Accumulator Timing in Gated Mode Selected Crystal CPU Clock Cycle Time (E/2 ) (E/214) 6 Common XTAL Frequencies 4.0 MHz 1.0 MHz 1000 ns 64.0 s 16.384 ms 8.0 MHz 2.0 MHz 500 ns 32.0 s 8.192 ms 12.0 MHz 3.0 MHz 333 ns 21.33 s 5.461 ms (E) (1/E) 1 count overflow - MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 101 Programmable Timer 8.7.1 Pulse Accumulator Control Register Four of the pulse accumulator control register (PACTL) bits control an 8-bit pulse accumulator system. Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system. Address: Read: Write: Reset: $0026 Bit 7 DDRA7 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 DDRA3 0 2 I4/O5 0 1 RTR1 0 Bit 0 RTR0 0 Figure 8-20. Pulse Accumulator Control Register (PACTL) DDRA7 -- Data Direction Control for Port A Bit 7 The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as general-purpose I/O or as an output compare. NOTE Even when port A bit 7 is configured as an output, the pin still drives the input to the pulse accumulator. Refer to Chapter 5 Input/Output (I/O) Ports for more information. PAEN -- Pulse Accumulator System Enable Bit 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD -- Pulse Accumulator Mode Bit 0 = Event counter 1 = Gated time accumulation PEDGE -- Pulse Accumulator Edge Control Bit This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 8-8. Table 8-8. Pulse Accumulator Edge Control PAMOD 0 0 1 1 PEDGE 0 1 0 1 Action on Clock PAI falling edge increments the counter. PAI rising edge increments the counter. A 0 on PAI inhibits counting. A 1 on PAI inhibits counting. DDRA3 -- Data Direction Register for Port A Bit 3 Refer to Chapter 5 Input/Output (I/O) Ports. I4/O5 -- Input Capture 4/Output Compare 5 Bit Refer to 8.3 Input Capture. RTR1 and RTR0 -- RTI Interrupt Rate Select Bits Refer to 8.5 Real-Time Interrupt. MC68HC711D3 Data Sheet, Rev. 2.1 102 Freescale Semiconductor Pulse Accumulator 8.7.2 Pulse Accumulator Count Register The 8-bit read/write pulse accumulator count register (PACNT) contains the count of external input events at the PAI input or the accumulated count. The counter is not affected by reset and can be read or written at any time. Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles. Address: Read: Write: Reset: $0027 Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset Figure 8-21. Pulse Accumulator Count Register (PACNT) 8.7.3 Pulse Accumulator Status and Interrupt Bits The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located within timer registers TMSK2 and TFLG2. PAOVI and PAOVF -- Pulse Accumulator Interrupt Enable and Overflow Flag The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To clear this status bit, write a 1 in the corresponding data bit position (bit 5) of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation and does not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which requires PAOVF to be polled by user software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware interrupt request is generated each time PAOVF is set. Before leaving the interrupt service routine, software must clear PAOVF by writing to the TFLG2 register. PAII and PAIF -- Pulse Accumulator Input Edge Interrupt Enable and Flag The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a 1 in the corresponding data bit position (bit 4). The PAII control bit allows configuring the pulse accumulator input edge detect for polled or interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII is 0, pulse accumulator input interrupts are inhibited, and the system operates in a polled mode. In this mode, the PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the interrupt service routine, software must clear PAIF by writing to the TFLG register. Address: Read: Write: Reset: $0024 Bit 7 TOI 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 0 0 2 0 0 1 PR1 0 Bit 0 PR0 0 Figure 8-22. Timer Interrupt Mask 2 Register (TMSK2) Address: Read: Write: Reset: $0025 Bit 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-23. Timer Interrupt Flag 2 Register (TFLG2) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 103 Programmable Timer MC68HC711D3 Data Sheet, Rev. 2.1 104 Freescale Semiconductor Chapter 9 Electrical Characteristics 9.1 Introduction This section contains electrical specifications. 9.2 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 9.5 DC Electrical Characteristics for guaranteed operating conditions. Rating Supply voltage Input voltage Current drain per pin(1) Excluding VDD, VSS, VRH, and VRL Storage temperature 1. One pin at a time, observing maximum power dissipation limits Symbol VDD VIn ID TSTG Value -0.3 to +7.0 -0.3 to +7.0 25 -55 to +150 Unit V V mA C NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 105 Electrical Characteristics 9.3 Functional Operating Temperature Range Rating Operating temperature range MC68HC711D3 MC68HC711D3V Symbol TA Value TL to TH -40 to +85 -40 to +105 Unit C 9.4 Thermal Characteristics Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 40-pin plastic dual in-line package (DIP) 44-pin plastic leaded chip carrier (PLCC) 44-pin plastic quad flat pack (QFP) Total power dissipation(1) Device internal power dissipation I/O pin power dissipation(2) A constant(3) Symbol TJ TA JA Value TA + (PD x JA) User-determined 50 50 85 PINT + PI/O K / TJ + 273C IDD x VDD User-determined PD x (TA + 273C) + JA x PD2 Unit C C C/W PD PINT PI/O K W W W W/C 1. This is an approximate value, neglecting PI/O. 2. For most applications, PI/O PINT and can be neglected. 3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of K to solve for PD and TJ, iteratively, for any value of TA. MC68HC711D3 Data Sheet, Rev. 2.1 106 Freescale Semiconductor DC Electrical Characteristics 9.5 DC Electrical Characteristics Characteristic(1) Output voltage(2) ILoad = 10.0 A Output high voltage(1) ILoad = - 0.8 mA, VDD = 4.5 V Output low voltage ILoad = 1.6 mA Input high voltage All outputs All outputs except RESET and MODA All outputs except RESET, EXTAL, and MODA All outputs except XTAL All inputs except RESET RESET Symbol VOL VOH VOH VOL VIH VIL IOZ IIn VSB ISB IDD -- -- -- -- WIDD -- -- -- -- SIDD -- -- -- -- 6 15 10 20 A 100 150 8 12 pF 15 27 27 35 mA Min -- VDD - 0.1 VDD - 0.8 -- 0.7 x VDD 0.8 x VDD VSS - 0.3 -- Max 0.1 -- -- 0.4 VDD + 0.3 VDD + 0.3 0.2 x VDD 10 Unit V V V V V A Input low voltage All inputs I/O ports, three-state leakage PA7, PA3, PC7-PC0, PD7-PD0, VIn = VIH or VIL MODA/LIR, RESET Input leakage current IRQ, XIRQ VIn = VDD or VSS VIn = VDD or VSS MODB/VSTBY RAM standby voltage RAM standby current Total supply current RUN: Single-chip mode dc -- 2 MHz dc -- 3 MHz Expanded multiplexed mode dc -- 2 MHz dc -- 3 MHz WAIT -- All peripheral functions shut down: Single-chip mode dc -- 2 MHz dc -- 3 MHz Expanded multiplexed mode dc -- 2 MHz dc -- 3 MHz STOP -- No clocks, single-chip mode: dc -- 2 MHz dc -- 3 MHz Input capacitancePA3-PA0, IRQ, XIRQ, EXTAL PA7, PC7-PC0, PD7-PD0, MODA/LIR, RESET Power dissipation Single-chip mode dc -- 2 MHz dc -- 3 MHz Expanded multiplexed mode dc -- 2 MHz dc -- 3 MHz EPROM programming voltage EPROM programming time (3) -- -- 4.0 -- Power down Power down 1 10 VDD 20 A V A mA CIn PD -- -- -- -- 11.75 2 85 150 150 195 12.75 4 mW VPP tPP V ms 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. VOH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification is not applicable to ports C and D in wired-OR mode. 3. All ports configured as inputs: VIL 0.2 V, VIH VDD -0.2 V; no dc loads; EXTAL is driven with a square wave; tcyc = 476.5 ns. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 107 Electrical Characteristics VDD EQUIVALENT TEST LOAD(1) Pins R2 PA3-PA7 PB0-PB7 PC0-PC7 PD0, PD5-PD7 E PD1--PD4 R1 3.26 K R2 2.38 K C1 90 pF TEST POINT C1 R1 3.26 K 2.38 K 200 pF Note: 1. Full test loads are applied during all ac electrical timing measurements. Figure 9-1. Equivalent Test Load ~ VDD 0.4 V ~ V SS NOM INPUTS 20% of VDD NOMINAL TIMING ~ VDD OUTPUTS ~ VSS DC TESTING VDD - 0.8 V 0.4 V 0.4 V NOM 70% of VDD CLOCKS, STROBES VDD - 0.8 V CLOCKS, STROBES ~ VDD 20% of VDD ~ VSS 20% of VDD SPEC 70% of VDD SPEC 70% of VDD 20% of VDD (NOTE 1) VDD - 0.8 V 0.4 V INPUTS SPEC TIMING ~ VDD OUTPUTS ~ VSS AC TESTING 70% of VDD 20% of VDD Note: 1. During ac timing measurements, inputs are driven to 0.4 volts and VDD - 0.8 volts while timing measurements are taken at the 20% and 70% of VDD points. Figure 9-2. Test Methods MC68HC711D3 Data Sheet, Rev. 2.1 108 Freescale Semiconductor Control Timing 9.6 Control Timing Characteristic(1) Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup timetPCSU = 1/4 tcyc + 50 ns Reset input pulse width(2) To guarantee external reset vector Minimum input time can be preempted by internal reset Mode programming setup time Mode programming hold time Interrupt pulse width, PWIRQ = tcyc + 20 ns IRQ edge-sensitive mode Wait recovery startup time Timer pulse width PWTIM = tcyc + 20 ns Input capture pulse Accumulator input 1.0 MHz Symbol Min fO tcyc fXTAL 4 fO tPCSU PWRSTL tMPS tMPH PWIRQ tWRS PWTIM dc 1000 -- dc 300 8 1 2 10 1020 -- 1020 Max 1.0 -- 4.0 4.0 -- -- -- -- -- -- 4 -- Min dc 500 -- dc 175 8 1 2 10 520 -- 520 Max 2.0 -- 8.0 8.0 -- -- -- -- -- -- 4 -- Min dc 333 -- dc 133 8 1 2 10 353 -- 353 Max 3.0 -- 12.0 12.0 -- -- -- -- -- -- 4 -- MHz ns MHz MHz ns tcyc tcyc ns ns tcyc ns 2.0 MHz 3.0 MHz Unit 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5 Input/Output (I/O) Ports for further details. PA0-PA3(1) PA0-PA3(2) PA7(1) (3) PWTIM PA7(2) (3) Notes: 1. Rising edge sensitive input 2. Falling edge sensitive input 3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2. Figure 9-3. Timer Inputs MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 109 110 VDD EXTAL 4064 tcyc E tPCSU PWRSTL RESET tMPS MODA, MODB NEW PC NEW PC tMPH Electrical Characteristics MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ADDRESS FFFE FFFE FFFE FFFE FFFF FFFE FFFE FFFE FFFE FFFE FFFF Figure 9-4. POR and External Reset Timing Diagram Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 111 RESET IRQ(1) PWIRQ IRQ(2) or XIRQ tSTOPDELAY(3) AS E ADDRESS(4) STOP ADDR STOP ADDR + 1 STOP ADDR + 1 OPCODE Resume program with instruction which follows the STOP instruction. ADDRESS(5) STOP ADDR STOP ADDR + 1 STOP ADDR + 1 STOP ADDR + 2 SP - 8 SP - 8 FFF2 (FFF4) FFF3 (FFF5) NEW PC Notes: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Edge sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4064 tcyc if DLY bit = 1 or 4 tcyc if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0) SP...SP-7 Figure 9-5. STOP Recovery Timing Diagram Control Timing 112 E tPCSU IRQ, XIRQ, OR INTERNAL INTERRUPTS WAIT ADDR WAIT ADDR + 1 Electrical Characteristics MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor tWRS SP SP - 1 SP - 2...SP - 8 SP - 8 SP - 8...SP - 8 SP - 8 SP - 8 SP - 8 VECTOR ADDR NEW PC VECTOR ADDR + 1 ADDRESS PCL PCH, YL, YH, XL, XH, A, B, CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 9-6. WAIT Recovery Timing Diagram Freescale Semiconductor (2) E tPCSU IRQ(1) PWIRQ IRQ , XIRQ OR INTERNAL INTERRUPT NEXT OP + 1 NEXT OPCODE AS SP SP - 1 SP - 3 SP - 4 SP - 6 SP - 8 SP - 8 VECTOR ADDR NEW PC VECTOR ADDR + 1 MC68HC711D3 Data Sheet, Rev. 2.1 113 ADDRESS SP - 2 SP - 5 SP - 7 ADDRESS OP CODE ---- PCL PCH IYL IYH IXL IXH B A CCR ---- VECT MSB VECT LSB OP CODE R/W Notes: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) Figure 9-7. Interrupt Timing Diagram Control Timing Electrical Characteristics 9.7 Peripheral Port Timing Characteristic(1) Frequency of operation (E-clock frequency) E-clock period Peripheral data setup time(2) MCU read of ports A, B, C, and D Peripheral data hold time(2) MCU read of ports A, B, C, and D Delay time, peripheral data write MCU write to port A MCU writes to ports B, C, and D tPWD = 1/4 tcyc + 150 ns 1.0 MHz Symbol Min fO tCYC tPDSU tPDH 1.0 1000 100 50 Max 1.0 -- -- -- Min 2.0 500 100 50 Max 2.0 -- -- -- Min 3.0 333 100 50 Max 3.0 -- -- -- MHz ns ns ns 2.0 MHz 3.0 MHz Unit tPWD -- -- 200 350 -- -- 200 225 -- -- 200 ns 183 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively). MCU WRITE TO PORT E t PWD PORTS B, C, D PREVIOUS PORT DATA NEW DATA VALID tPWD PORT A PREVIOUS PORT DATA NEW DATA VALID Figure 9-8. Port Write Timing Diagram MCU READ OF PORT E tPDSU PORTS A, B, C, D tPDH Figure 9-9. Port Read Timing Diagram MC68HC711D3 Data Sheet, Rev. 2.1 114 Freescale Semiconductor Expansion Bus Timing 9.8 Expansion Bus Timing Num Characteristic(1) Frequency of operation (E-clock frequency) 1 2 3 4A 4B 9 12 17 18 19 21 22 24 25 26 27 28 29 35 36 Cycle time Pulse width, E low, PWEL = 1/2 tcyc -- 23 ns Pulse width, E high, PWEH = 1/2 tcyc - 28 ns E and AS rise time E and AS fall time Address hold time(2)a, tAH = 1/8 tcyc - 29.5 ns Non-muxed address valid time to E rise tAV = PWEL - (tASD + 80 ns)(2)a Read data setup time Read data hold time (max = tMAD) Write data delay time, tDDW = 1/8 tcyc + 65.5 ns(2)a Symbol fO tcyc PWEL PWEH tr tf tAH tAV tDSR tDHR tDDW tDHW tAVM tASL tAHL tASD PWASH tASED tACCA tACCE tMAD 1.0 MHz Min dc 1000 477 472 -- -- 95.5 281.5 30 0 -- 95.5 271.5 151 95.5 115.5 221 115.5 744.5 -- 145.5 Max 1.0 -- -- -- 20 20 -- -- -- 145.5 190.5 -- -- -- -- -- -- -- -- 442 -- 2.0 MHz dc 500 227 222 -- -- 33 94 30 0 -- 33 84 26 33 53 96 53 307 -- 83 2.0 -- -- -- 20 20 -- -- -- 83 128 -- -- -- -- -- -- -- -- 192 -- 3.0 MHz dc 333 146 141 -- -- 26 54 30 0 -- 26 54 13 31 31 63 31 196 -- 51 3.0 -- -- -- 20 15 -- -- -- 51 71 -- -- -- -- -- -- -- -- 111 -- Min Max Min Max Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write data hold time, tDHW = 1/8 tcyc - 29.5 ns(2)a Muxed address valid time to E rise tAVM = PWEL - (tASD + 90 ns)(2)a Muxed address valid time to AS fall tASL = PWASH - 70 ns Muxed address hold time, tAHL = 1/8 tcyc - 29.5 ns(2)b Delay time, E to AS rise, tASD = 1/8 tcyc - 9.5 ns(2)a Pulse width, AS high, PWASH = 1/4 tcyc - 29 ns Delay time, AS to E rise, tASED = 1/8 tcyc - 9.5 ns(2)b MPU address access tACCA = tcyc - (PWEL- tAVM) - tDSR - tf MPU access time , tACCE = PWEH - tDSR Muxed address delay (previous cycle MPU read) tMAD = tASD + 30 ns(2)a(3) time(2)a 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 tCYC in the above formulas, where applicable: (a) (1-dc) x 1/4 tCYC (b) dc x 1/4 tCYC Where: DC is the decimal value of duty cycle percentage (high time). 3. Formula only for dc to 2 MHz. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 115 Electrical Characteristics 1 2 E 4 12 R/W, ADDRESS (NON-MUX) 36 READ ADDRESS/DATA (MULTIPLEXED) WRITE ADDRESS 25 4 AS 26 27 28 24 4 22 29 ADDRESS 19 DATA DATA 21 35 17 18 4 9 3 Note: Measurement points shown are 20% and 70% of VDD. Figure 9-10. Multiplexed Expansion Bus Timing Diagram MC68HC711D3 Data Sheet, Rev. 2.1 116 Freescale Semiconductor Serial Peripheral Interface Timing 9.9 Serial Peripheral Interface Timing Num Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master(2) Slave Enable lag time Master(2) Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data valid (after enable edge)(3) Data hold time (outputs) (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic(1) Symbol 2.0 MHz Min Max dc dc 2.0 500 -- 250 -- 250 340 190 340 190 100 100 100 100 0 -- -- 0 -- -- -- -- 0.5 2.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 240 -- 100 2.0 100 2.0 3.0 MHz Min Max dc dc 2.0 333 -- 240 -- 240 227 127 227 127 100 100 100 100 0 -- -- 0 -- -- -- -- 0.5 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 167 167 -- 100 2.0 100 2.0 Unit fop(m) fop(s) tcyc(m) tCYC(s) tlead(m) tlead(s) tlag(m) tlag(s) tw(SCKH)m tw(SCKH)s tw(SCKL)m tw(SCKL)s tsu(m) tsu(s) th(m) th(s) ta tdis tv(s) tho trm trs tfm tfs fop MHz tcyc ns ns 2 3 ns 4 ns 5 ns 6 ns 7 ns 8 9 10 11 12 ns ns ns ns ns s ns s 13 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 117 Electrical Characteristics SS (INPUT) SS IS HELD HIGH ON MASTER 1 5 12 13 SCK (CPOL = 0) (OUTPUT) SEE NOTE 4 5 13 12 SEE NOTE 4 MSB IN 10 (REF) 11 MASTER MSB OUT 13 BIT 6 - - - -1 BIT 6 - - - -1 10 LSB IN 11 (REF) MASTER LSB OUT 12 SCK (CPOL = 1) (OUTPUT) MISO (INPUT) MOSI (OUTPUT) Note: This first clock edge is generated internally but is not seen at the SCK pin. Figure 9-11. SPI Master Timing (CPHA = 0) SS (INPUT) SS IS HELD HIGH ON MASTER 1 5 13 12 SEE NOTE 4 5 13 SEE NOTE 4 MSB IN 10 (REF) 11 MASTER MSB OUT 13 BIT 6 - - - -1 12 BIT 6 - - - -1 10 6 LSB IN 11 (REF) MASTER LSB OUT 12 7 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) MOSI (OUTPUT) Note: This last clock edge is generated internally but is not seen at the SCK pin. Figure 9-12. SPI Master Timing (CPHA = 1) MC68HC711D3 Data Sheet, Rev. 2.1 118 Freescale Semiconductor Serial Peripheral Interface Timing SS (INPUT) 1 5 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BIT 6 - - - -1 4 5 4 BIT 6 - - - -1 11 LSB IN 13 12 3 12 13 SLAVE LSB OUT 11 9 SEE NOTE Note: Not defined but normally MSB of character just received Figure 9-13. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 5 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SEE NOTE 10 SLAVE 6 MOSI (INPUT) MSB IN 4 5 4 MSB OUT 7 BIT 6 - - - -1 10 BIT 6 - - - -1 11 LSB IN 12 13 3 13 12 9 SLAVE LSB OUT Note: Not defined but normally LSB of character previously transmitted Figure 9-14. SPI Slave Timing (CPHA = 1) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 119 Electrical Characteristics MC68HC711D3 Data Sheet, Rev. 2.1 120 Freescale Semiconductor Chapter 10 Ordering Information and Mechanical Specifications 10.1 Introduction This section provides ordering information for the MC68HC711D3. In addition, mechanical specifications are provided for the following packaging options: * 40-pin plastic dual in-line package (DIP) * 44-pin plastic leaded chip carrier (PLCC) * 44-pin plastic quad flat pack (QFP) 10.2 Ordering Information Table 10-1. MC Order Numbers MC Order Number Package Type 40-pin DIP 44-pin PLCC -40 to +105C 44-pin QFP -40 to +85C MC68HC711D3VFN2 MC68HC711D3CFB2 MC68HC711D3VFN3 MC68HC711D3CFB3 Temperature 2 MHz -40 to +85C -40 to +85C MC68HC711D3CP2 MC68HC711D3CFN2 3 MHz MC68HC711D3CP3 MC68HC711D3CFN3 10.3 40-Pin DIP (Case 711-03) NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 40 21 B 1 20 A N L C J H G F D K SEATING PLANE M DIM A B C D F G H J K L M N MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 121 Ordering Information and Mechanical Specifications 10.4 44-Pin PLCC (Case 777-02) D B 0.007(0.180) M T U L-M S NS NS -N- Y BRK 0.007(0.180) M T L-M S Z -L-M- V 44 1 W D X VIEW D-D G1 0.010 (0.25) S T L-M S NS A R Z 0.007(0.180) M T 0.007(0.180) M T L-M S L-M S NS NS H 0.007(0.180) M T L-M S NS J E C G -TG1 0.010 (0.25) S T L-M S NS VIEW S VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF THE MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMINSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940124). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635). K1 0.004 (0.10) SEATING PLANE K F 0.007(0.180) M T L-M S NS INCHES DIM A B C E F G H J K R U V W X Y Z G1 K1 MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.610 0.630 0.040 MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 15.50 16.00 1.02 MC68HC711D3 Data Sheet, Rev. 2.1 122 Freescale Semiconductor 44-Pin QFP (Case 824A-01) 10.5 44-Pin QFP (Case 824A-01) B L B 33 34 23 22 S -A-, -B-, -DD D S DETAIL A F BASE METAL S C A-B 0.05 (0.002) A-B -AL -BB M V 0.20 (0.008) 0.20 (0.008) M H A-B S J D N DETAIL A 44 1 11 12 0.20 (0.008) M C A-B S D S SECTION B-B NOTES: 1. 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 2. CONTROLLING DIMENSION: MILLIMETER. 3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MILLIMETERS DIM MIN MAX A 9.90 10.10 B 9.90 10.10 C 2.10 2.45 D 0.30 0.45 E 2.00 2.10 F 0.30 0.40 G 0.80 BSC H --0.25 J 0.13 0.23 K 0.65 0.95 L 8.00 REF M 5 10 N 0.13 0.17 Q 0 7 R 0.13 0.30 S 12.95 13.45 T 0.13 --U 0 --V 12.95 13.45 W 0.40 --X 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC --- 0.010 0.005 0.009 0.026 0.037 0.315 REF 5 10 0.005 0.007 0 7 0.005 0.012 0.510 0.530 0.005 --0 --0.510 0.530 0.016 --0.063 REF -DA 0.20 (0.008) M C A-B S D S 0.05 (0.002) A-B S 0.20 (0.008) M H A-B S D M S DETAIL C CE -CSEATING PLANE -HH DATUM PLANE 0.01 (0.004) G M M T DATUM PLANE -H- R K W X DETAIL C Q MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 123 Ordering Information and Mechanical Specifications MC68HC711D3 Data Sheet, Rev. 2.1 124 Freescale Semiconductor Appendix A MC68HC11D3 and MC68HC11D0 A.1 Introduction The MC68HC11D3 and MC68HC11D0 are read-only memory (ROM) based high-performance microcontrollers (MCU) based on the MC68HC11E9 design. Members of the Dx series are derived from the same mask and feature a high-speed multiplexed bus capable of running at up to 3 MHz and a fully static design that allows operations at frequencies to dc. The only difference between the MCUs in the Dx series is whether the ROM has been tested and guaranteed. The information contained in this document applies to both the MC68HC11D3 and MC68HC11D0 with the differences given in this appendix. Features of the MC68HC11D3 and MC68HC11D0 include: * 4 Kbytes of on-chip ROM (MC68HC11D3) * 0 bytes of on-chip ROM (MC68HC11D0) * 192 bytes of on-chip random-access memory (RAM) all saved during standby * 16-bit timer system: - Three input capture (IC) channels - Four output compare (OC) channels - One IC or OC software-selectable channel * 32 input/output (I/O) pins: - 26 bidirectional I/O pins - 3 input-only pins - 3 output-only pins * Available in these packages: - 44-pin plastic leaded chip carrier (PLCC) - 44-pin quad flat pack (QFP) MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 125 MC68HC11D3 and MC68HC11D0 A.2 Block Diagram MODA/LIR MODB/VSTBY RESET IRQ XIRQ XTAL EXTAL E OSCILLATOR MODE CONTROL PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 INTERRUPT CONTROL CLOCK LOGIC MC68HC11D3 -- 4 KBYTES ROM MC68HC11D0 -- 0 BYTES ROM PORT A COP PAI/OC1 PULSE ACCUMULATOR OC2/OC1 OC3/OC1 OC4/OC1 TIMER IC4/OC5/OC1 IC1 IC2 IC3 PERIODIC INTERRUPT 192 BYTES RAM SERIAL PERIPHERAL INTERFACE (SPI) MOSI MISO SCK SERIAL COMMUNICATIONS INTERFACE (SCI) VDD VSS EVSS SS MC68HC11D3 CPU CORE TxD RxD MULTIPLEXED ADDRESS/DATA BUS A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 A15 A14 A13 A12 A11 A10 A9 A8 DATA DIRECTION REGISTER B PORT B DATA DIRECTION REGISTER C PORT C DATA DIRECTION REGISTER D PORT D PD5 PD4 PD3 PD2 PD1 Figure A-1. MC68HC11D3 Block Diagram MC68HC711D3 Data Sheet, Rev. 2.1 126 Freescale Semiconductor PD7/R/W PD6/AS PD0 Pin Assignments A.3 Pin Assignments MODB/VSTBY 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 PD4/SCK PA6/OC2 PA5/OC3 PA4/OC4 PA3/IC4/OC5/OC1 PD3/MOSI PD2/MISO PA7/PAI PA2/IC1 PD5/SS VDD 28 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7 NC PA0/IC3 PA1/IC2 34 MODB MODA/LIR 35 MODA 41 EXTAL 43 EXTAL XTAL 44 EVSS PC3 PC2 PC1 PC0 VSS 6 5 4 3 2 PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 XIRQ PD7/R/W PD6/AS RESET IRQ PD0/RxD PD1/TxD 7 8 9 10 11 12 13 14 15 16 17 Figure A-2. Pin Assignments for 44-Pin PLCC 1 XTAL 38 EVSS PC3 PC2 PC1 PC0 VSS 43 42 41 40 39 37 36 E 42 E PC4 PC5 PC6 PC7 XIRQ PD7 PD6 RESET IRQ PD0 PD1 1 2 3 4 5 6 7 8 9 10 12 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC PA0 PA1 32 31 30 29 28 27 26 25 24 13 14 15 16 17 18 19 20 21 PA3 23 VDD PA7 PA6 PA5 PA4 PD2 PD3 PD4 Figure A-3. Pin Assignments for 44-Pin QFP MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 127 PD5 PA2 MC68HC11D3 and MC68HC11D0 A.4 Memory Map $0000 $0000 INTERNAL REGISTERS AND I/O (CAN BE MAPPED TO ANY 4-K BOUNDARY $003F USING INIT REGISTER) $0040 192 BYTES STATIC RAM (CAN BE MAPPED TO ANY 4-K BOUNDARY $00FF USING THE INIT REGISTER) $7000 4 KBYTES ROM (MC68HC11D3) PRESENT AT RESET AND CAN BE DISABLED BY $7FFF ROM ON BIT IN CONFIG REGISTER. INTERRUPT VECTORS ARE EXTERNAL. EXTERNAL EXTERNAL $B000 $BF00 $BFFF 4-KBYTES ROM $7000 $8000 BOOT ROM $BFC0 SPECIAL MODES INTERRUPT $BFFF VECTORS $FF00 $FFFF SINGLE CHIP EXPANDED SPECIAL MULTIPLEXED BOOTSTRAP SPECIAL TEST $FFFF $FFC0 NORMAL MODES INTERRUPT $FFFF VECTORS Figure A-4. MC68HC11Dx(1) Memory Map A.5 MC68HC11D3 and MC68HC11D0 Electrical Characteristics The parameters given in Chapter 9 Electrical Characteristics apply to the MC68HC11D3 and MC68HC11D0 with the exceptions given here. A.5.1 Functional Operating Temperature Range Rating Operating temperature range MC68HC11D0C Symbol TA Value TL to TH -40 to +85 Unit C A.5.2 Thermal Characteristics Characteristic Package thermal resistance (junction-to-ambient) 44-pin plastic leaded chip carrier (PLCC) 44-pin plastic quad flat pack (QFP Symbol JA Value 50 85 Unit C/W 1. MC68HC11D0 only operates in expanded multiplexed mode and bootstrap mode. MC68HC711D3 Data Sheet, Rev. 2.1 128 Freescale Semiconductor Ordering Information A.6 Ordering Information MC Order Number MCU MC68HC11D3 (Custom ROM) MC68HC11D0 (No ROM) Package Temperature 2 MHz 44-pin PLCC 44-pin PLCC 44-pin QFP -40 to +85C -40 to +85C -40 to +85C MC68HC11D3CFN2 MC68HC11D0CFN2 MC68HC11D0CFB2 3 MHz MC68HC11D3CFN3 MC68HC11D0CFN3 MC68HC11D0CFB3 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 129 MC68HC11D3 and MC68HC11D0 MC68HC711D3 Data Sheet, Rev. 2.1 130 Freescale Semiconductor Appendix B MC68L11D0 B.1 Introduction The MC68L11D0 is an extended-voltage version of the MC68HC11D0 microcontroller that can operate in applications that require supply voltages as low as 3.0 volts. Operation is identical to that of the MC68HC11D0 (see Appendix A MC68HC11D3 and MC68HC11D0) in all aspects other than electrical parameters, as shown in this appendix. Features of the MC68HC11D0 include: * Suitable for battery-powered portable and hand-held applications * Excellent for use in devices such as remote sensors and actuators * Operating performance is same at 5 V and 3 V B.2 MC68L11D0 Electrical Characteristics The parameters given in Chapter 9 Electrical Characteristics apply to the MC68L11D0 with the exceptions given here. B.2.1 Functional Operating Temperature Range Rating Operating temperature range Symbol TA Value TL to TH -20 to +70 Unit C B.2.2 DC Electrical Characteristics Characteristic(1) Output voltage(2) All outputs except XTAL ILoad = 10.0 AAll outputs except XTAL, RESET, and MODA Output high voltage(1) All outputs except XTAL, RESET, and MODA ILoad = - 0.5 mA, VDD = 3.0 V ILoad = - 0.8 mA, VDD = 4.5 V Output low voltage All outputs except XTAL ILoad = 1.6 mA, VDD = 5.0 V ILoad = 1.0 mA, VDD = 3.0 V Symbol VOL VOH VOH Min -- VDD - 0.1 VDD - 0.8 Max 0.1 -- -- Unit V V VOL -- 0.4 V The dc electrical table continues on next page. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 131 MC68L11D0 Characteristic(1) Input high voltage All inputs except RESET RESET Input low voltage All inputs I/O ports, three-state leakage PA7, PA3, PC7-PC0, VIn = VIH or VIL PD7-PD0, MODA/LIR, RESET Input leakage current VIn = VDD or VSS PA2-PA0, IRQ, XIRQ VIn = VDD or VSS MODB/VSTBY RAM standby voltagePower down RAM standby currentPower down Input capacitancePA2-PA0, IRQ, XIRQ, EXTAL PA3, PA7, PC7-PC0, PD7-PD0, MODA/LIR, RESET Output load capacitanceAll outputs except PD4-PD1 PD4-PD1 Total supply current(3) RUN: Single-chip mode VDD = 5.5 V VDD = 3.0 V Expanded multiplexed mode VDD = 5.5 V VDD = 3.0 V WAIT -- All peripheral functions shut down: Single-chip mode VDD = 5.5 V VDD = 3.0 V Expanded multiplexed mode VDD = 5.5 V VDD = 3.0 V STOP -- No clocks, single-chip mode: VDD = 5.5 V VDD = 3.0 V Power dissipation Single-chip mode VDD = 5.5 V VDD = 3.0 V Expanded multiplexed mode VDD = 5.5 V VDD = 3.0 V Symbol VIH VIL IOZ Min 0.7 x VDD 0.8 x VDD VSS - 0.3 -- Max VDD + 0.3 VDD + 0.3 0.2 x VDD 10 Unit V V A IIn VSB ISB CIn CL -- -- 2.0 -- -- -- -- -- 1 10 VDD 10 8 12 90 100 A V A pF pF IDD 8 4 14 7 WIDD 3 1.5 5 2.5 SIDD 50 25 6 3 10 5 15 8 27 14 mA mA A 50 25 PD 44 12 77 21 85 24 150 42 mW 1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. VOH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification is not applicable to ports C and D in wired-OR mode. 3. EXTAL is driven with a square wave, and tcyc = 1000 ns for 1 MHz rating; tcyc = 500 ns for 2 MHz rating; VIL 0.2 V; VIH VDD - 0.2 V; No dc loads MC68HC711D3 Data Sheet, Rev. 2.1 132 Freescale Semiconductor MC68L11D0 Electrical Characteristics B.2.3 Control Timing Characteristic(1) Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time tPCSU = 1/4 tcyc + 50 ns Reset input pulse width(2) To guarantee external reset vector Minimum input time can be preempted by internal reset Interrupt pulse width, PWIRQ = tcyc + 20 ns IRQ edge-sensitive mode Wait recovery startup time Timer pulse width PWTIM = tcyc + 20 ns Input capture pulse accumulator input Symbol fO tcyc fXTAL 4 fO tPCSU 1.0 MHz Min dc 1000 -- dc 325 Max 1.0 -- 4.0 4.0 -- 2.0 MHz Min dc 500 -- dc 200 Max 2.0 -- 8.0 8.0 -- Unit MHz ns MHz MHz ns PWRSTL 8 1 1020 -- 1020 -- -- -- 4 -- 8 1 520 -- 520 -- -- -- 4 -- tcyc PWIRQ tWRS PWTIM ns tcyc ns 1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 4 Resets, Interrupts, and Low-Power Modes for further details. B.2.4 Peripheral Port Timing Characteristic(1) Frequency of operation (E-clock frequency) E-clock period Peripheral data setup time(2) MCU read of ports A, B, C, and D Peripheral data hold time(2) MCU read of ports A, B, C, and D Delay time, peripheral data write MCU write to port A MCU writes to ports B, C, and D tPWD = 1/4 tcyc + 150 ns Symbol fO tcyc tPDSU tPDH 1.0 MHz Min dc 1000 100 50 Max 1.0 -- -- -- dc 500 100 50 2.0 MHz Min Max 2.0 -- -- -- Unit MHz ns ns ns tPWD -- -- 200 350 -- -- 200 ns 225 1. VDD = 3.0 Vd to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively). MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 133 MC68L11D0 B.2.5 Expansion Bus Timing Num Characteristic(1) Frequency of operation (E-clock frequency) 1 2 3 4A 4B 9 12 17 18 19 21 22 24 25 26 27 28 29 35 36 Cycle time Pulse width, E low, PWEL = 1/2 tcyc -- 23 ns Pulse width, E high, PWEH = 1/2 tcyc - 28 ns E and AS rise time E and AS fall time Address hold time(2)a, tAH = 1/8 tcyc - 29.5 ns Non-muxed address valid time to E rise tAV = PWEL - (tASD + 80 ns)(2)a Read data setup time Read data hold time (max = tMAD) Write data delay time, tDDW = 1/8 tcyc + 65.5 ns(2)a Symbol fO tcyc PWEL PWEH tr tf tAH tAV tDSR tDHR tDDW tDHW tAVM tASL tAHL tASD PWASH tASED tACCA tACCE tMAD 1.0 MHz Min dc 1000 475 470 -- -- 95 275 30 0 -- 95 265 150 95 120 220 120 735 -- 150 Max 1.0 -- -- -- 25 25 -- -- -- 150 195 -- -- -- -- -- -- -- -- 440 -- 2.0 MHz Min dc 500 225 220 -- -- 33 88 30 0 -- 33 78 25 33 58 95 58 298 -- 88 Max 2.0 -- -- -- 25 25 -- -- -- 88 133 -- -- -- -- -- -- -- -- 190 -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write data hold time, tDHW = 1/8 tcyc - 29.5 ns(2)a Muxed address valid time to E rise tAVM = PWEL - (tASD + 90 ns)(2)a Muxed address valid time to AS fall tASL = PWASH - 70 ns Muxed address hold time, tAHL = 1/8 tcyc - 29.5 ns(2)b Delay time, E to AS rise, tASD = 1/8 tcyc - 9.5 ns(2)a Pulse width, AS high, PWASH = 1/4 tcyc - 29 ns Delay time, AS to E rise, tASED = 1/8 tcyc - 9.5 ns(2)b MPU address access time(2)a tACCA = tcyc - (PWEL- tAVM) - tDSR - tf MPU access time , tACCE = PWEH - tDSR Muxed address delay (previous cycle MPU read) tMAD = tASD + 30 ns(2)a 1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 tCYC in the above formulas, where applicable: (a) (1-dc) x 1/4 tCYC (b) dc x 1/4 tCYC Where: DC is the decimal value of duty cycle percentage (high time). MC68HC711D3 Data Sheet, Rev. 2.1 134 Freescale Semiconductor MC68L11D0 Electrical Characteristics B.2.6 Serial Peripheral Interface Timing Num Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master(2) Slave Enable lag time Master(2) Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data valid (after enable edge)(3) Data hold time (outputs) (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic(1) Symbol 1.0 MHz Min Max dc dc 2.0 1000 -- 500 -- 500 680 380 680 380 100 100 100 100 0 -- -- 0 -- -- -- -- 0.5 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 240 -- 100 2.0 100 2.0 2.0 MHz Min Max dc dc 2.0 500 -- 250 -- 250 340 190 340 190 100 100 100 100 0 -- -- 0 -- -- -- -- 0.5 2.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 240 -- 100 2.0 100 2.0 Unit fop(m) fop(s) tcyc(m) tCYC(s) tlead(m) tlead(s) tlag(m) tlag(s) tw(SCKH)m tw(SCKH)s tw(SCKL)m tw(SCKL)s tsu(m) tsu(s) th(m) th(s) ta tdis tv(s) tho trm trs tfm tfs fop MHz tcyc ns ns 2 3 ns 4 ns 5 ns 6 ns 7 ns 8 9 10 11 12 ns ns ns ns ns s ns s 13 1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Signal production depends on software. 3. Assumes 100 pF load on all SPI pins. MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor 135 MC68L11D0 B.3 Ordering Information Package 44-pin PLCC 44-pin QFP Frequency 2 MHz 2 MHz Features No ROM No ROM MC Order Number MC68L11D0FN2 MC68L11D0FB2 MC68HC711D3 Data Sheet, Rev. 2.1 136 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. MC68HC711D3 Rev. 2.1, 07/2005 |
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